MikeBartley

About Mike Bartley

Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification. Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP. Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions:

Alpinum AI provides tools and automations using Artificial Intelligence to help companies reduce development costs (by up to 90%!)

Alpinum Services provides RTL to GDS VLSI services from nearshore and offshore centres in Vietnam, India, Egypt, Eastern Europe, Mexico and Costa Rica.

Alpinum Consulting also provides strategic board level consultancy services, helping companies to grow.

Alpinum training department provides self-paced, fully online training in System Verilog, UVM Introduction and Advanced, Formal Verification, DV methodologies for SV, UVM, VHDL and OSVVM and CPU/RISC-V.

Alpinum Events organises a number of free-to-attend industry events

You can contact Mike (mike@alpinumconsulting.com or +44 7796 307958) or book a meeting with Mike using Calendly (https://calendly.com/mike-alpinumconsulting).

Inside the UK FPGA Landscape: Insights from the DESN Industry Survey 2025
Inside the UK FPGA Landscape: Insights from the DESN Industry Survey 2025

2025 FPGA, Blogs, FPGA Front Runner

Inside the UK FPGA Landscape: Insights from the DESN Industry Survey 2025

By Mike Bartley|2026-01-25T04:49:49+00:009th December 2025|2025 FPGA, Blogs, FPGA Front Runner|

The DESN community at TechWorks, together with its FPGA Front [...]

Why We Need Chiplets: The Challenges Facing the Semiconductor Industry and How They Help
Why We Need Chiplets: The Challenges Facing the Semiconductor Industry and How They Help

Blogs, General

Why We Need Chiplets: The Challenges Facing the Semiconductor Industry and How They Help

By Mike Bartley|2026-01-25T04:45:09+00:0013th November 2025|Blogs, General|

The semiconductor industry is under growing pressure to deliver higher [...]

Alpinum Blog Writing Services: Turning Technical Insight into Industry Influence
Alpinum Blog Writing Services: Turning Technical Insight into Industry Influence

Case Studies

Alpinum Blog Writing Services: Turning Technical Insight into Industry Influence

By Mike Bartley|2025-10-31T10:11:30+00:0022nd October 2025|Case Studies|

Introduction: Writing That Communicates Complex Engineering Clearly Effective communication is [...]

RISC-V Test Generation: Using Random and Directed Stimulus to Achieve Coverage Closure
RISC-V Test Generation: Using Random and Directed Stimulus to Achieve Coverage Closure

RISC-V

RISC-V Test Generation: Using Random and Directed Stimulus to Achieve Coverage Closure

By Mike Bartley|2026-01-25T04:44:58+00:0021st October 2025|RISC-V|

Introduction Design verification of RISC-V processors presents unique challenges. The [...]

Functional Coverage for RISC-V Verification: A Verification-First Approach
Functional Coverage for RISC-V Verification: A Verification-First Approach

RISC-V

Functional Coverage for RISC-V Verification: A Verification-First Approach

By Mike Bartley|2026-01-25T04:45:12+00:0014th October 2025|RISC-V|

Introduction: Why Coverage is the True Metric Verification engineers understand [...]

RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug

RISC-V

RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug

By Mike Bartley|2026-01-25T04:51:00+00:007th October 2025|RISC-V|

Introduction As a verification engineer working on RISC-V designs, I’ve [...]

RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug

Blogs, RISC-V

RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug

By Mike Bartley|2026-01-25T04:38:38+00:001st October 2025|Blogs, RISC-V|

Introduction As a verification engineer working on RISC-V designs, I’ve [...]

Compliance, Certification and Verification: Compare and Contrast
Compliance, Certification and Verification: Compare and Contrast

Blogs, RISC-V

Compliance, Certification and Verification: Compare and Contrast

By Mike Bartley|2026-01-25T04:38:44+00:0019th September 2025|Blogs, RISC-V|

Introduction For semiconductor and embedded software stakeholders, clarity around compliance, [...]

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