Low-Power Verification Training

From Power-Aware RTL and UPF to Complete SoC Verification Sign-Off

Develop the practical skills needed to verify reliable, energy-efficient semiconductor designs across RTL, CPU, firmware and complete System-on-Chip environments.

This live online programme progresses from power-intent verification and power-aware RTL through software-controlled power management to formal verification, coverage closure and production sign-off.

Live Online | 3 Parts | 6 Sessions | 24 Training Hours

Programme at a Glance

The programme contains two four-hour sessions in each part and provides a complete learning path from block-level verification to SoC sign-off.

Course Overview

Modern semiconductor designs use power gating, isolation, retention, multiple voltage domains and Dynamic Voltage and Frequency Scaling to reduce energy consumption.

These techniques also introduce verification challenges during shutdown, start-up, state restoration, voltage transitions and software-controlled power changes.

This training gives engineers a practical understanding of:

• Unified Power Format
• Power-aware simulation
• UVM and SystemVerilog Assertions
• CPU and firmware power management
• Dynamic Voltage and Frequency Scaling
• Power Management Unit verification
• Hardware/software co-verification
• Formal verification
• Functional and power coverage
• Verification planning and sign-off

The programme uses practical demonstrations, real-world examples and structured verification workflows.

Training Schedule and Registration

What You Will Learn

By completing the programme, participants will be able to:

• Learn how power intent is specified, implemented, and verified using UPF
• Apply power-aware verification methodologies using UVM, SVA, and simulation-based workflows
• Verify isolation, retention, level shifters, and power domain interactions
• Explore DVFS and CPU power management verification techniques
• Understand firmware-controlled power management and software interaction
• Learn how Power Management Units (PMUs) coordinate power states across modern SoCs
• Verify suspend, resume, and wake-up sequences across multiple power domains
• Apply formal verification techniques to validate low-power architectures
• Develop verification plans and sign-off strategies for production-ready low-power designs

These outcomes cover the full low-power verification lifecycle from RTL to SoC integration.

Course Structure

Part 1: Low-Power Foundations and Power-Aware RTL Verification

Build a strong foundation in low-power design and learn how power intent is implemented and verified at RTL level.

Topics include:

• Low-power design fundamentals
• Unified Power Format
• Power domains
• Clock and power gating
• Isolation cells
• Retention registers
• Level shifters
• Power-aware simulation
• UVM and SystemVerilog Assertions
• Power-intent debugging

Part 2: CPU, Firmware and Low-Power Software Verification

Understand how processors, firmware, operating systems and Power Management Units coordinate power management.

Topics include:

• Dynamic Voltage and Frequency Scaling
• CPU power states
• Firmware-controlled power management
• PMU architecture
• Suspend and resume
• Wake-up validation
• Peripheral power management
• Linux power management
• Hardware/software co-verification
• Firmware debugging

Part 3: SoC Power Management, Formal Verification and Sign-Off

Learn how low-power verification scales across complete multi-domain SoCs and progresses towards verification closure.

Topics include:

• SoC power architecture
• Multi-domain verification
• Cross-domain interactions
• Power-aware formal verification
• Functional and power coverage
• Verification planning
• Coverage closure
• Sign-off requirements
• Silicon correlation
• End-to-end verification workflows

Who Should Attend?

This training is designed for:

• Design Verification and UVM Engineers
• RTL, ASIC, SoC and FPGA Engineers
• Embedded Software and Firmware Engineers
• CPU and Low-Power Verification Engineers
• Power Architecture Engineers
• Verification Managers and Technical Leads
• Technical Leads responsible for low-power design and verification

Training Format

• Live online instructor-led training
• Three progressive learning modules
• Two consecutive training sessions per part
• Four hours of live instruction per session
• Interactive demonstrations and practical walkthroughs
• Real-world semiconductor case studies
• Hands-on verification methodologies and debugging techniques
• Interactive Q&A sessions and technical discussions

What Is Included?

• Live instructor-led online training
• Digital course materials
• Practical demonstrations
• Real-world semiconductor examples
• Interactive technical discussions and Q&A
• Certificate of Completion

Key Benefits

✔ Develop practical expertise in modern low-power verification methodologies

✔ Learn how to verify UPF implementations across RTL, CPU, and SoC levels

✔ Gain confidence using power-aware UVM, SVA, and simulation workflows

✔ Understand firmware, PMU, and operating system interaction with hardware power management

✔ Build practical skills in DVFS, power gating, isolation, and retention verification

✔ Learn formal verification and coverage methodologies for low-power designs

✔ Improve verification efficiency using structured planning and sign-off workflows

✔ Strengthen your expertise in developing reliable, energy-efficient semiconductor systems

Frequently Asked Questions

Can I register for one part only?

Yes. Each part can be booked separately for $60.

How long is the complete programme?

The full programme includes six four-hour sessions, providing 24 hours of live training.

Is the training delivered online?

Yes. All sessions are delivered live online.

Will participants receive a certificate?

Yes. A Certificate of Completion is included.