The Alpinum Online Submission Portal provides a structured environment for running practical semiconductor verification exercises as part of Alpinum’s training and engineering learning workflows. It allows engineers to configure verification jobs, select supported EDA tool flows, run prepared examples, upload custom scripts or designs, review execution logs and download results.
The portal roadmap includes Formal Verification, AI in DV, RISC-V Verification and future Analog workflows, supporting controlled training access and approved verification use rather than open public playground access.
AI in DV Training-Run Demos
AlpinumDV supports AI-assisted verification workflows through targeted simulation, rapid feedback, coverage improvement and debug support. The public-facing training-run demos below show example AlpinumDV use cases within the Online Submission Portal, including test-plan generation, UVM support, coverage closure, reference-model support, protocol examples and RISC-V verification demos.
AlpinumDV (AI) Online Submission Tool: Training-Run Demos
| Day | Demo / Example | Design Class | AlpinumDV App |
|---|---|---|---|
| 1 | Spec-to-Testplan Mapping | Any | Test-Plan Gen |
| 1 | Cookbook-Compliance Review | Any | UVM Cookbook + UVC Layout |
| 2 | Effort-Level Control | Any | Depth (smoke/standard/exhaustive) |
| 2 | Adder / Adder32 | Combinational | TB Gen + Coverage |
| 3 | Up/Down Counter | Sequential | TB Gen + Coverage |
| 3 | Coverage Closure / Analyzer | Any | Coverage Oracle |
| 3 | Synchronous FIFO | Memory / CDC | Scoreboard + Coverage |
| 4 | ALU (spec-only ref) | Combinational | AI Reference Model |
| 4 | Single / Dual-Port RAM | Memory | Read-Latency Reference |
| 5 | Bug-Injected (adder_bugs / counter_bugs) | Bug detection | Root-Cause Analysis |
| 5 | APB Slave | Bus protocol | Handshake SB + Reg-map Cov |
| 6 | Reference-Model Modes | Any | User / AI-gen / Ref-as-DUT |
| 6 | SPI (OpenCores) | Serial protocol | Registered-Read Reference + SVA |
| 6 | RISC-V Single-Cycle (headline) | CPU / ISA | AI Reference + ProGen + Deep Coverage |
Formal Verification Training-Run Demos
The Formal Verification training-run demos for the Online Submission Portal cover structured examples across Synopsys VC Formal and Cadence Jasper Gold application flows. These demos support hands-on learning, formal app selection, guided execution and practical exposure to formal verification workflows through Alpinum’s online tooling environment.
Alpinum Online Submission Tool: Training-Run Demos
| Day | Demo / Example | VC Formal App (using AI Advisor) | Jasper Gold App (in AI Advisor) |
|---|---|---|---|
| 1 | Synchronous FIFO | FPV | FPV |
| 1 | X-Propagation | XPROP | FXP |
| 2 | ALU | DPV | DPV |
| 2 | Reachability | COI | COV |
| 3 | Up/Down Counter | FPV | FPV |
| 3 | Two-Transaction FIFO | FPV | FPV |
| 3 | Formal Coverage Analyzer (FCA) | COV (FCA) | COV |
| 4 | SelAB | FPV | FPV |
| 4 | Connectivity Checking (CC) | CONN | CC |
| 4 | Formal Low Power (FLP) + Testbench Analyzer (FTA) | LPV | FLP + FTA |
| 5 | RISC-V Single-Cycle | FPV | FPV |
| 5 | Formal Security (FSV) + Functional Safety (FuSa) | FSV | FSV + FuSa |
| 5 | APB4 | FPV | FPV |
| 6 | Arbiter | FPV | FPV |
| 6 | Traffic-Light FSM | FPV | FPV |
| 6 | DPV & FRV | DPV + CSR | DPV + FRV |
| 6 | SVA-to-Req Mapping | FPV | FPV |
RISC-V Verification Demo Roadmap
The RISC-V roadmap for the Online Submission Portal includes block-level and CPU-level verification demos covering CVA6 CPU blocks, RISC-V single-cycle CPU blocks, dynamic simulation, formal verification, RISCV-DV, Spike ISS comparison, coverage reports and portal-based result viewing.
RISC-V Submission Portal Tool: Test Demos
| # | Category | Demo / Example | Verification Flow | Output / Report | Date |
|---|---|---|---|---|---|
| Block-Level Verification — CVA6 CPU Blocks (UVM + VCS/Xcelium + FPV) | |||||
| 1 | CVA6 Block | Integer Divider | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 2 | CVA6 Block | Integer Multiplier | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 3 | CVA6 Block | Compressed Decoder | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 4 | CVA6 Block | CSR Reg-File | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 5 | CVA6 Block | Commit Stage | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 6 | CVA6 Block | Instruction Queue | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 7 | CVA6 Block | Main Decoder | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 8 | CVA6 Block | Load-Store Unit | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 9 | CVA6 Block | Floating-Point Unit | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 10 | CVA6 Block | Scoreboard Demo | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 11 | CVA6 Block | Branch Unit | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 12 | CVA6 Block | Translation Lookaside Buffer | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| Block-Level Verification — RISC-V Single-Cycle CPU Blocks (UVM + VCS/Xcelium + FPV) | |||||
| 13 | Single-Cycle Block | Instruction Fetch Stage | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 14 | Single-Cycle Block | Control Unit | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 15 | Single-Cycle Block | Instruction Decoder | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 16 | Single-Cycle Block | Register File | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 17 | Single-Cycle Block | ALU | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 18 | Single-Cycle Block | Extend Block | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 19 | Single-Cycle Block | Cache in Memory Subsystem | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| 20 | Single-Cycle Block | Write Back Stage | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | |
| CPU-Level Verification — RISC-V Toolchain (RISCV-DV, Spike ISS) | |||||
| 21 | CVA6 CPU | Arithmetic Instruction Test (RISCV-DV generated) | RISCV-DV ISG → Spike ISS + VCS | Spike vs. RTL Comparison + Coverage Report | |
Analog and AMS Verification Demo Roadmap
The Analog and AMS roadmap for the Online Submission Portal includes practical demo workflows for Analog IC Design using Python, AMS co-simulation, Verilog-AMS/SystemVerilog-AMS/UVM-AMS and future power-aware AMS examples. These demos support structured training, guided execution and practical engineering learning through Alpinum’s online tooling environment.
Analog IC Design Using Python: Demo Roadmap
| # | Category | Demo / Example | Software / Tool | Output / Deliverable |
|---|---|---|---|---|
| 1 | Analog IC Design Using Python | Python Environment & LUT Generation | Python (Colab) | LUT Generator |
| 2 | Analog IC Design Using Python | NMOS LUT-Based Characterization | Python (Colab) | Characterization of NMOS devices |
| 3 | Analog IC Design Using Python | Graph of the parasitic capacitance Cgg | Python (Colab) | Plot & Report |
| 4 | Analog IC Design Using Python | From Specification to Transistor Width Using LUTs | Python (Colab) | Extract ID/W from the LUT and calculate W |
| 5 | Analog IC Design Using Python | Add new cell to get the graph of the parasitic capacitance, Vdssat and Vov on the same graph | Python (Colab) | Combined Plot |
| 6 | Analog IC Design Using Python | Design the input pairs of the fully differential folded cascode OTA | Python (Colab) | Design real example |
AMS Co-Simulation (RNM & UVM): Demo Roadmap
| # | Category | Demo / Example | Software / Tool | Output / Deliverable | Delivery Date |
|---|---|---|---|---|---|
| 1 | AMS Co-Simulation (RNM & UVM) | RC Circuit Design | Xschem | Schematic + Simulation | |
| 2 | AMS Co-Simulation (RNM & UVM) | RC Circuit Simulation | Xschem | Waveforms result & netlist | |
| 3 | AMS Co-Simulation (RNM & UVM) | CMOS Inverter Design Using PDK | Xschem | Inverter design | 11 Aug 2026 |
| 4 | AMS Co-Simulation (RNM & UVM) | Comparator Simulation | Xschem | Comparator using Verilog-A | 11 Aug 2026 |
| 5 | AMS Co-Simulation (RNM & UVM) | UVM-AMS Smoke Test & Transcript Walk-through | Cadence | UVM-AMS Smoke Test | 18 Aug 2026 |
| 6 | AMS Co-Simulation (RNM & UVM) | Interactive Mixed-Signal Waveform Debug | Cadence | Waveform Debug | 18 Aug 2026 |
Verilog-AMS, SystemVerilog-AMS & UVM-AMS: Demo Roadmap
| # | Category | Demo / Example | Software / Tool | Output / Deliverable | Delivery Date |
|---|---|---|---|---|---|
| 1 | Verilog-AMS, SystemVerilog-AMS & UVM-AMS | Benefits of Top-Down Approach | Python / Xschem | Design using Top-Down Approach | |
| 2 | Verilog-AMS, SystemVerilog-AMS & UVM-AMS | Create resistor.va and capacitor.va models | Python / Xschem | Verilog-A Device Models | |
| 3 | Verilog-AMS, SystemVerilog-AMS & UVM-AMS | RC Circuit Simulation | Python / Xschem | Mixed-Signal RC Demo | |
| 4 | Verilog-AMS, SystemVerilog-AMS & UVM-AMS | Logic-to-Analog Adapter | Python / Xschem | Adapter Demonstration | |
| 5 | Verilog-AMS, SystemVerilog-AMS & UVM-AMS | UVM-AMS Smoke Test & Transcript Walk-through | Cadence | UVM-AMS Smoke Test | |
| 6 | Verilog-AMS, SystemVerilog-AMS & UVM-AMS | Interactive Mixed-Signal Waveform Debug | Cadence | Waveform Debug |
AMS Co-Simulation (Power-Aware / UPF): Demo Roadmap
| # | Category | Demo / Example | Software / Tool | Output / Deliverable | Delivery Date |
|---|---|---|---|---|---|
| 1 | AMS Co-Simulation (Power-Aware / UPF) | Develop the Complete Course from Scratch — Session 1 | Course Development | Slides, Demos & Labs | 1 Sep 2026 |
| 2 | AMS Co-Simulation (Power-Aware / UPF) | Develop the Complete Course from Scratch — Session 1 | Course Development | Slides, Demos & Labs | 1 Sep 2026 |
| 3 | AMS Co-Simulation (Power-Aware / UPF) | Develop the Complete Course from Scratch — Session 2 | Course Development | Slides, Demos & Labs | 8 Sep 2026 |
| 4 | AMS Co-Simulation (Power-Aware / UPF) | Develop the Complete Course from Scratch — Session 2 | Course Development | Slides, Demos & Labs | 8 Sep 2026 |
| 5 | AMS Co-Simulation (Power-Aware / UPF) | Develop the Complete Course from Scratch — Session 3 | Course Development | Slides, Demos & Labs | 15 Sep 2026 |
Built for Structured Training
The Alpinum Online Submission Portal is designed for structured training and controlled verification workflows. Access is connected to Alpinum training, approved learning pathways or agreed monthly access, so users can work through guided formal verification exercises in the right technical and licensing environment.
