The Alpinum Online Submission Portal provides a structured environment for running practical semiconductor verification exercises as part of Alpinum’s training and engineering learning workflows. It allows engineers to configure verification jobs, select supported EDA tool flows, run prepared examples, upload custom scripts or designs, review execution logs and download results.
The portal roadmap includes Formal Verification, AI in DV, RISC-V Verification and future Analog workflows, supporting controlled training access and approved verification use rather than open public playground access.
AI in DV Training-Run Demos
AlpinumDV supports AI-assisted verification workflows through targeted simulation, rapid feedback, coverage improvement and debug support. The public-facing training-run demos below show example AlpinumDV use cases within the Online Submission Portal, including test-plan generation, UVM support, coverage closure, reference-model support, protocol examples and RISC-V verification demos.
AlpinumDV (AI) Online Submission Tool: Training-Run Demos
| Day | Demo / Example | Design Class | AlpinumDV App |
|---|---|---|---|
| 1 | Spec-to-Testplan Mapping | Any | Test-Plan Gen |
| 1 | Cookbook-Compliance Review | Any | UVM Cookbook + UVC Layout |
| 2 | Effort-Level Control | Any | Depth (smoke/standard/exhaustive) |
| 2 | Adder / Adder32 | Combinational | TB Gen + Coverage |
| 3 | Up/Down Counter | Sequential | TB Gen + Coverage |
| 3 | Coverage Closure / Analyzer | Any | Coverage Oracle |
| 3 | Synchronous FIFO | Memory / CDC | Scoreboard + Coverage |
| 4 | ALU (spec-only ref) | Combinational | AI Reference Model |
| 4 | Single / Dual-Port RAM | Memory | Read-Latency Reference |
| 5 | Bug-Injected (adder_bugs / counter_bugs) | Bug detection | Root-Cause Analysis |
| 5 | APB Slave | Bus protocol | Handshake SB + Reg-map Cov |
| 6 | Reference-Model Modes | Any | User / AI-gen / Ref-as-DUT |
| 6 | SPI (OpenCores) | Serial protocol | Registered-Read Reference + SVA |
| 6 | RISC-V Single-Cycle (headline) | CPU / ISA | AI Reference + ProGen + Deep Coverage |
Formal Verification Training-Run Demos
The Formal Verification training-run demos for the Online Submission Portal cover structured examples across Synopsys VC Formal and Cadence Jasper Gold application flows. These demos support hands-on learning, formal app selection, guided execution and practical exposure to formal verification workflows through Alpinum’s online tooling environment.
Alpinum Online Submission Tool: Training-Run Demos
| Day | Demo / Example | VC Formal App (using AI Advisor) | Jasper Gold App (in AI Advisor) |
|---|---|---|---|
| 1 | Synchronous FIFO | FPV | FPV |
| 1 | X-Propagation | XPROP | FXP |
| 2 | ALU | DPV | DPV |
| 2 | Reachability | COI | COV |
| 3 | Up/Down Counter | FPV | FPV |
| 3 | Two-Transaction FIFO | FPV | FPV |
| 3 | Formal Coverage Analyzer (FCA) | COV (FCA) | COV |
| 4 | SelAB | FPV | FPV |
| 4 | Connectivity Checking (CC) | CONN | CC |
| 4 | Formal Low Power (FLP) + Testbench Analyzer (FTA) | LPV | FLP + FTA |
| 5 | RISC-V Single-Cycle | FPV | FPV |
| 5 | Formal Security (FSV) + Functional Safety (FuSa) | FSV | FSV + FuSa |
| 5 | APB4 | FPV | FPV |
| 6 | Arbiter | FPV | FPV |
| 6 | Traffic-Light FSM | FPV | FPV |
| 6 | DPV & FRV | DPV + CSR | DPV + FRV |
| 6 | SVA-to-Req Mapping | FPV | FPV |
RISC-V Verification Demo Roadmap
The RISC-V roadmap for the Online Submission Portal includes block-level and CPU-level verification demos covering CVA6 CPU blocks, RISC-V single-cycle CPU blocks, dynamic simulation, formal verification, RISCV-DV, Spike ISS comparison, coverage reports and portal-based result viewing.
RISC-V Submission Portal Tool: Test Demos
| # | Category | Demo / Example | Verification Flow | Output / Report | Date |
|---|---|---|---|---|---|
| Block-Level Verification — CVA6 CPU Blocks (UVM + VCS/Xcelium + FPV) | |||||
| 1 | CVA6 Block | Integer Divider | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Mon 20 Jul 2026 |
| 2 | CVA6 Block | Integer Multiplier | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Mon 20 Jul 2026 |
| 3 | CVA6 Block | Compressed Decoder | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Mon 20 Jul 2026 |
| 4 | CVA6 Block | CSR Reg-File | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Mon 20 Jul 2026 |
| 5 | CVA6 Block | Commit Stage | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Tue 21 Jul 2026 |
| 6 | CVA6 Block | Instruction Queue | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Tue 21 Jul 2026 |
| 7 | CVA6 Block | Main Decoder | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Tue 21 Jul 2026 |
| 8 | CVA6 Block | Load-Store Unit | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Tue 21 Jul 2026 |
| 9 | CVA6 Block | Floating-Point Unit | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Wed 22 Jul 2026 |
| 10 | CVA6 Block | Scoreboard Demo | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Wed 22 Jul 2026 |
| 11 | CVA6 Block | Branch Unit | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Wed 22 Jul 2026 |
| 12 | CVA6 Block | Translation Lookaside Buffer | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Wed 22 Jul 2026 |
| Block-Level Verification — RISC-V Single-Cycle CPU Blocks (UVM + VCS/Xcelium + FPV) | |||||
| 13 | Single-Cycle Block | Instruction Fetch Stage | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Thu 23 Jul 2026 |
| 14 | Single-Cycle Block | Control Unit | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Thu 23 Jul 2026 |
| 15 | Single-Cycle Block | Instruction Decoder | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Thu 23 Jul 2026 |
| 16 | Single-Cycle Block | Register File | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Thu 23 Jul 2026 |
| 17 | Single-Cycle Block | ALU | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Fri 24 Jul 2026 |
| 18 | Single-Cycle Block | Extend Block | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Fri 24 Jul 2026 |
| 19 | Single-Cycle Block | Cache in Memory Subsystem | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Fri 24 Jul 2026 |
| 20 | Single-Cycle Block | Write Back Stage | UVM + VCS/Xcelium (Dynamic) + VC Formal (FPV) | Coverage Report (Verdi) + UVM Console/Scoreboard + FPV Console | Fri 24 Jul 2026 |
| CPU-Level Verification — RISC-V Toolchain (RISCV-DV, Spike ISS) | |||||
| 21 | CVA6 CPU | Arithmetic Instruction Test (RISCV-DV generated) | RISCV-DV ISG → Spike ISS + VCS | Spike vs. RTL Comparison + Coverage Report | Mon 27 Jul 2026 |
Built for Structured Training
The Alpinum Online Submission Portal is designed for structured training and controlled verification workflows. Access is connected to Alpinum training, approved learning pathways or agreed monthly access, so users can work through guided formal verification exercises in the right technical and licensing environment.
