Semiconductor Verification Training Courses: UVM, Formal, RISC-V, FPGA and AI in DV

As someone who drives teams using pre-silicon emulation on an FPGA as part of our validation coverage, I identified a need to familiarise myself with Design Verification to cover more breadth and identify ways to improve our processes. Related to the sessions, the pace was adequate, and the presenter built up basic concepts through more advanced topics, allowing live and on-demand trainees to follow up and make the most of it. The exercises and tools available to run them were good. I got a chance to cover the theory and play around with some blocks and test benches to confirm the learning in the course. The quality of the material is more than I expected for quick training. It goes to the point of ensuring that trainees use their time to learn concepts that are used in verification engineers’ day-to-day tasks. Response time from the instructor and support team was good for the inquiries made. I did propose an improvement on the quizzes, which are extensive and fully cover the material, with questions that require some thought on my part. However, the course would benefit from an additional, shorter quiz as a quick refresher for the student.

In summary, the course perfectly matched my requirements and gave an excellent return on my time.

As a Senior Engineer at Intel, I’ve attended various technical training courses over the years, but this one stood out for its structure and practical relevance. The content was thoughtfully designed — progressing logically from foundational concepts to advanced applications — and always linked directly to real project situations. The sessions were highly engaging and effective because they combined theory, live demonstrations, and hands-on exercises. The instructor clearly understood the realities of complex hardware projects and was able to translate that experience into practical guidance. The course also included regular checkpoints and exercises, reinforcing understanding and encouraging discussion.

Overall, this course was extremely valuable. It was well-paced, expertly delivered, and immediately applicable to engineering challenges.

Working in a fast-paced product environment, I value concise, relevant, and directly applicable training, and this course delivered precisely that. The sessions were well organised and covered key principles, complex examples, and system-level discussions. The instructor combined deep technical expertise with strong communication skills, making advanced topics clear and accessible. The exercises, quizzes, and examples made the learning process active rather than passive, and the flexible schedule allowed me to balance project work alongside the training.

It’s a course for anyone looking to enhance their skills and stay current with the latest practices in verification and design.

Coming from a digital design and verification background, I sought a course to strengthen my theoretical knowledge and practical application skills. This training achieved precisely that. The material was clearly presented, comprehensive, and supported by relevant examples that reflected real engineering scenarios. The course structure made it easy for new and experienced engineers to follow. I particularly appreciated the interactive nature of the sessions and the opportunity to discuss best practices with the instructor. The mix of lectures, exercises, and assessments helped consolidate learning effectively.

The quality of both the content and the delivery was excellent. I highly recommend this program to engineering teams looking to improve their verification and design capabilities efficiently.

As a university student focusing on digital systems and embedded design, I was keen to explore modern engineering practices used in industry. This course provided an excellent foundation for that. The training combined a strong theoretical base with practical application through exercises, simulations, and examples from real-world engineering challenges. The course delivery was clear and engaging, and the online learning platform made it easy for me 3 to review material and receive feedback at my own pace.

This training complemented the university curriculum, effectively connecting academic knowledge with the realities of industry practice. It’s an outstanding resource for students looking to enhance their university experience.

The Design Verification (DV) course (delivered by Dr. Mike Bartley) met our main objective which was to upskill our graduate and junior verification engineers to have the knowledge and understanding of verification to start supporting projects in the shortest time possible whilst minimising initial training and supervision time from our senior engineers.

The Design Verification course (delivered by TechWorks Academy) met our main objective which was to upskill our graduate engineers to have the knowledge and understanding of the application of VHDL and OSVVM in verification environments, the course also covered SV and UVM. Course understanding was helped with the extensive set of examples and exercises which allowed the participants to progress from initially simple, to complex design and test benches – which included debug and fix.

It was s great opportunity to learn from someone who has a vast knowledge and industrial experience in CPU’s, SOC’s, and software (down to assembler), and their verification. Part1 of the course is an introduction to CPU concepts and an overview of state-of-the-art CPU verification practices. Personally, my introduction to mutation testing and constrained pseudo-random stimulus generation techniques for CPU’s by taking this course were completely new things and justified the cost of the course by themselves, even though they represent less than 10% of the content!. Each lecture in the course has both quizzes and forms which helped to ensure that I understood both the concepts and their application in real-world context.