Build faster, scalable mixed-signal verification workflows using AMS co-simulation, Real Number Modelling, SystemVerilog and UVM methodologies. This practical AMS Co-Simulation (RNM & UVM) Training helps design verification and mixed-signal engineers understand how analog and digital simulation environments work together, how Real Number Modelling (RNM) can accelerate mixed-signal verification, and how UVM methodologies can be integrated into scalable AMS testbenches.
Progress from co-simulation fundamentals and behavioural modelling through RNM abstraction, compilation flows, UVM integration and advanced mixed-signal debugging.
Build Scalable Mixed-Signal Verification with RNM and UVM
Modern semiconductor systems increasingly combine analog functions with complex digital control and verification environments. The resulting verification challenge is not simply to simulate an analog block and a digital block independently. Engineers need a practical way to model their interactions, synchronise analog and digital simulation domains, select appropriate levels of abstraction and integrate those models into repeatable verification environments. Full transistor-level or continuous-time simulation can provide valuable fidelity, but it may not always provide the execution speed required for large regression environments.
This is where Real Number Modelling (RNM) becomes important. RNM allows selected analog behaviour to be represented at a higher level of abstraction so that mixed-signal functionality can be exercised within more digital-centric verification flows. Combined with UVM, this can support verification environments that are faster, more reusable and easier to scale. This training develops that capability from the foundations of AMS co-simulation through RNM methodology to practical UVM integration and debugging.
Course Overview
The AMS Co-Simulation (RNM & UVM) Training programme provides a structured introduction to mixed-signal verification environments that bring together analog behavioural models, SPICE, Verilog-A/Verilog-AMS, SystemVerilog RNM and UVM. The programmer begins with the fundamentals of mixed-signal simulation and the interaction between analog and digital simulation engines. Participants then progress into AMS compilation flows, connect modules, hierarchy mapping, power-aware concepts and SystemVerilog Real Number Modelling, including resolution functions and abstraction techniques.
The final session connects RNM with UVM-based verification, covering UVM-AMS architecture, drivers, monitors, interfaces, mixed-signal waveform generation and practical debugging. A Mixed-Signal SAR ADC Verification Lab brings the concepts together in a representative verification exercise.
For current availability and registration, visit the Alpinum Training page.
Course at a glance
| Area | Details |
|---|---|
| Delivery | Live, instructor-led online training |
| Structure | 3 progressive training sessions |
| Duration | 3 × 2-hour sessions · 6 hours total |
| Core focus | AMS co-simulation, RNM and UVM-based mixed-signal verification |
| Mixed-signal modelling | Verilog-A, Verilog-AMS and SPICE concepts |
| RNM methodology | SystemVerilog RNM, nettype real, resolution functions and abstraction |
| Compilation & connectivity | VCS-AD flow, connect modules and hierarchy mapping |
| UVM integration | UVM-AMS architecture, drivers, monitors, interfaces and RNM testbench integration |
| Debug focus | FSDB generation, Verdi AMS, convergence and X-propagation analysis |
| Practical exercise | Mixed-Signal SAR ADC Verification Lab |
What You Will Learn
By completing this AMS co-simulation training programme, participants will develop practical understanding of how mixed-signal models and digital verification methodology can be combined within a scalable verification workflow.
- Understand AMS co-simulation architectures
- Distinguish between analog continuous-time and digital event-driven simulation concepts
- Understand how analog and digital simulation engines interact
- Work with Verilog-A and Verilog-AMS concepts in mixed-signal environments
- Understand the role of SPICE models within AMS verification
- Apply analog behavioural modelling approaches
- Understand AMS compilation and connectivity flows
- Work with connect modules and hierarchy mapping
- Understand the role of RNM in accelerating mixed-signal verification
- Apply SystemVerilog Real Number Modelling
- Understand nettype real concepts
- Work with resolution functions
- Use abstraction techniques to improve verification scalability
- Understand key power-aware AMS concepts within the co-simulation flow
- Integrate RNM models into a UVM-based testbench
- Understand UVM-AMS architecture
- Work with UVM drivers, monitors and interfaces in an AMS context
- Generate mixed-signal FSDB data
- Use structured mixed-signal debugging techniques
- Analyse convergence and X-propagation problems
Apply the overall methodology through a Mixed-Signal SAR ADC verification exercise
Who Should Attend?
This programme is designed for engineers working across digital, analog and mixed-signal verification domains. It is particularly relevant for:
- Design Verification Engineers
- AMS / Mixed-Signal Engineers
- UVM Verification Engineers
- RTL Engineers moving into AMS verification
- Verification Leads and Architects
It can be especially useful for engineers who already understand digital verification concepts and now need to work more effectively with analog models, mixed-signal simulation or RNM-based abstraction.
Looking for the next course date?
Upcoming AMS training dates and current registration options are maintained on our main Training page.
Why AMS Co-Simulation Matters
Mixed-signal systems combine behaviours that are naturally represented using different simulation approaches. Digital verification typically relies on event-driven simulation. Analog and transistor-level behaviour, by contrast, may require continuous-time or SPICE-based simulation. An AMS co-simulation environment brings these domains together so interactions between them can be verified within a coordinated simulation flow.
This introduces several engineering questions: Which behaviour should remain analog? Which behaviour can be abstracted? How should analog and digital engines synchronise? How are signals translated between domains? How should behavioural models be integrated? How can the resulting environment be incorporated into an existing UVM flow? How should engineers debug failures that span both analog and digital domains? This course builds the knowledge needed to approach those questions systematically.
Why Real Number Modelling Matters
Real Number Modelling provides an abstraction strategy for representing selected analog behaviour in a form that can execute efficiently in a digital-centric simulation environment. Instead of solving every electrical behaviour at transistor or continuous-time level, engineers can model the aspects of analog behaviour needed for a particular verification objective.
The benefit is not simply faster simulation. The deeper engineering objective is to select the right abstraction level so the model retains the behaviour required for verification while making large-scale test execution more practical. Alpinum’s course applies RNM specifically within a broader AMS co-simulation + UVM integration workflow.
From Analog Models to Scalable UVM Verification
The course follows a deliberately progressive structure.
- Understand the co-simulation environment: Learn how analog and digital simulation concepts differ and how Verilog-A, Verilog-AMS and SPICE-based behaviour fit into AMS simulation.
- Introduce abstraction and RNM: Understand compilation, connectivity and SystemVerilog RNM techniques that can make mixed-signal verification more scalable.
- Integrate with UVM and debug: Connect RNM and AMS models with structured UVM verification, waveform generation and debugging workflows.
Core workflow: Analog / mixed-signal behaviour → AMS co-simulation → behavioural abstraction → Real Number Modelling → UVM testbench integration → simulation and regression → mixed-signal debug.
Course Structure
Session 1: AMS Co-Simulation Fundamentals
Understand how analog and digital simulation environments work together
The first session establishes the fundamentals of mixed-signal co-simulation. Participants explore the difference between event-driven and continuous-time simulation before examining how analog behavioural models and SPICE-based concepts interact with digital verification environments.
Topics covered:
- Mixed-signal simulation concepts
- Event-driven versus continuous-time simulation
- Verilog-AMS fundamentals
- Verilog-A fundamentals
- SPICE modelling basics
- Analog behavioural modelling
- Digital / analog simulation-engine synchronisation
Practical focus: Build a clear understanding of the different simulation domains and how they interact within an AMS co-simulation environment.
Session 2: Compilation, Power & RNM
Use Real Number Modelling and abstraction to improve mixed-signal verification scalability
The second session moves from basic co-simulation into the infrastructure and abstraction techniques required to construct a practical verification environment. Participants examine AMS compilation and connectivity before progressing into SystemVerilog Real Number Modelling.
Topics covered:
- VCS-AD compilation flow
- Connect modules
- Hierarchy mapping
- UPF and power-aware AMS concepts
- SystemVerilog RNM methodology
- nettype real
- Resolution functions
- Abstraction techniques
- Simulation optimisation concepts
Practical focus: Understand how RNM and appropriate abstraction can improve mixed-signal simulation performance while supporting scalable verification workflows.
Session 3: UVM Integration & Debug
Bring mixed-signal models into a structured UVM verification environment
The third session focuses on applying UVM methodology to AMS verification and building a practical debug workflow. Participants explore UVM-AMS architecture and RNM testbench integration before moving into waveform generation and mixed-signal debug.
Topics covered:
- UVM-AMS architecture
- UVM drivers
- UVM monitors
- UVM interfaces
- RNM testbench integration
- Mixed-signal FSDB generation
- Verdi AMS debugging
- Convergence analysis
- X-propagation analysis
Practical focus: Connect AMS and RNM models to a reusable UVM verification environment and apply structured techniques to mixed-signal failures.
Capstone Exercise: Mixed-Signal SAR ADC Verification Lab
The programme includes a Mixed-Signal SAR ADC Verification Lab that brings together the techniques introduced across the three sessions. The exercise provides a representative context for considering analog behaviour, digital control, behavioural modelling, RNM abstraction, UVM-based stimulus and observation, mixed-signal simulation and structured debugging. This practical capstone positions the course as a verification programme rather than a purely conceptual introduction to RNM.
Analog / Digital Co-Simulation
AMS co-simulation allows analog and digital behaviour to execute within a coordinated verification flow. Participants learn the fundamental distinction between continuous-time and event-driven simulation and how those domains can interact.
Verilog-A and Verilog-AMS
Verilog-A and Verilog-AMS provide behavioural modelling mechanisms relevant to analog and mixed-signal systems. This course introduces them as components of the broader co-simulation workflow. Do not turn this page into a detailed Verilog-AMS language tutorial because the separate Verilog-AMS, SystemVerilog-AMS & UVM-AMS Training page should own that intent.
SPICE Modelling
SPICE remains an important reference point for analog circuit behaviour. The programme introduces SPICE modelling concepts so engineers can understand where circuit-level simulation fits into a mixed-signal verification architecture.
SystemVerilog Real Number Modelling
SystemVerilog RNM provides mechanisms for representing selected analog behaviour within a more digital-centric verification flow. The approved syllabus specifically includes SystemVerilog RNM methodology, nettype real, resolution functions and abstraction techniques. This combination gives the page a strong long-tail SEO target around SystemVerilog RNM mixed-signal verification training.
Connect Modules and Hierarchy Mapping
Interfaces between analog and digital models must be represented correctly for a mixed-signal environment to behave as intended. Connect modules and hierarchy mapping therefore form an important part of the compilation and integration workflow covered in Session 2.
Resolution Functions
When multiple values or drivers contribute to a real-number representation, the verification environment needs rules for resolving those values. Resolution functions are therefore part of the RNM methodology covered in the approved course.
UVM for Mixed-Signal Verification
UVM provides established architecture and reuse patterns for digital verification. In this programme, participants examine how these concepts extend into mixed-signal verification environments. The syllabus includes UVM-AMS architecture together with drivers, monitors, interfaces and RNM testbench integration. The goal is to understand how mixed-signal behaviour can participate in a structured, scalable verification methodology.
Mixed-Signal Debug and Convergence Analysis
AMS failures can be difficult to diagnose because the root cause may lie in analog behaviour, digital stimulus, abstraction, connectivity, model interaction, simulation convergence or X-propagation. The final session introduces FSDB generation, Verdi AMS debugging, convergence analysis and X-propagation analysis to help engineers investigate these failures systematically.
RNM vs Detailed Analog Simulation
Real Number Modelling should not be positioned as a universal replacement for SPICE or detailed analog modelling. The appropriate model depends on the verification objective. Detailed analog simulation may be appropriate when electrical accuracy is essential. RNM can be valuable when the required behaviour can be represented at a higher abstraction level and verification throughput or integration with digital regressions becomes important. This distinction keeps the page technically credible and avoids overselling RNM.
Training Format
Live Online Training: Instructor-led technical training delivered online.
Three Progressive Sessions: The programme progresses from co-simulation fundamentals to RNM and then UVM integration and debugging.
Six Hours Total: 3 × 2-hour sessions · 6 hours total.
Practical Verification Context: Technical concepts are connected to mixed-signal verification workflows rather than presented only as language definitions.
Capstone Exercise: The course concludes with a Mixed-Signal SAR ADC Verification Lab.
Key Benefits
- Build stronger understanding of AMS co-simulation architectures
- Understand analog/digital simulator interaction
- Develop practical familiarity with Verilog-A, Verilog-AMS and SPICE concepts
- Learn how RNM can improve mixed-signal verification execution
- Understand SystemVerilog nettype real
- Apply resolution functions and abstraction techniques
- Understand connect-module and hierarchy-mapping concepts
- Integrate RNM into UVM-based verification
- Build more scalable mixed-signal testbench architectures
- Develop stronger mixed-signal debug workflows
- Investigate convergence and X-propagation issues more systematically
Supporting Hands-On AMS Training Resources
Alpinum’s Online Submission Portal lists several related training demonstrations associated with AMS Co-Simulation (RNM & UVM), including:
- RC Circuit Design
- RC Circuit Simulation
- CMOS Inverter Design Using a PDK
- Comparator Simulation using Verilog-A
- UVM-AMS Smoke Test and Transcript Walk-through
- Interactive Mixed-Signal Waveform Debug
Position these as related AMS training resources and demonstrations unless Magdy confirms that every item is included in this exact course.
How This Course Differs from Alpinum’s Other AMS Training
| Course | Primary Focus | Core Journey |
|---|---|---|
| AMS Co-Simulation (RNM & UVM) | RNM abstraction, scalable co-simulation, UVM integration and mixed-signal debugging. | AMS fundamentals → RNM → UVM → debug |
| Verilog-AMS, SystemVerilog-AMS & UVM-AMS | Mixed-signal modelling languages, SystemVerilog-AMS connectivity and object model, and UVM-AMS methodology. | Verilog-AMS → SystemVerilog-AMS → UVM-AMS |
| AMS Co-Simulation (Power-Aware / UPF) | Explicit power intent, voltage domains, isolation, level shifting and PA-UVM. | AMS + UPF → power boundaries → PA-UVM → debug |
How This Course Fits into Alpinum’s AMS Training Path
Alpinum’s main Training hub groups four courses under Analog and Mixed-Signal (AMS) Training:
- Analog IC Design Using Python — analog IC design, gm/ID methodology, Python and transistor-sizing workflows.
- AMS Co-Simulation (RNM & UVM) — scalable mixed-signal verification using RNM and UVM.
- Verilog-AMS, SystemVerilog-AMS & UVM-AMS — AMS modelling languages and verification methodology.
- AMS Co-Simulation (Power-Aware / UPF) — power-aware mixed-signal systems and UPF.
Related AMS Engineering Expertise
Alpinum’s wider Analog & Mixed-Signal capability includes mixed-signal verification planning, model selection, analog/digital interaction checks, RNM/UVM-based flows and power-aware AMS co-simulation. That existing service page is therefore one of the strongest internal-link sources for this new training page.
Frequently Asked Questions
Build Faster, More Scalable AMS Verification Workflows
Develop practical capability across AMS co-simulation, behavioural modelling, SystemVerilog RNM, UVM integration and mixed-signal debugging. Progress from simulation fundamentals to RNM abstraction and reusable UVM-based verification.
