The standard programme contains 24 connected modules. It develops practical capability from CPU architecture and instruction-stream generation through RISC-V CPU verification and complete SoC verification.

Part 1 CPU and RISC-V Basics

Build the processor architecture and CPU-verification foundation, then apply it through functional coverage and riscv-dv exercises.

Module 1 Introduction to CPU

Understand instruction set architectures, CPU architecture and the operation of a simple CPU microarchitecture.

Module 2 How We Verify a CPU

Compare hierarchical CPU verification strategies across unit, processor and SoC integration levels using SystemVerilog, UVM, binary code, assembler and instruction-stream generation.

Module 3 Basic CPU Verification and Tooling

Learn constrained-random instruction generation, the role of an instruction-stream generator, open-source riscv-dv workflows and the verification impact of custom instructions.

Module 4 CPU Microarchitectures for Faster Execution

Compare RISC, CISC and VLIW approaches and connect microarchitecture choices to performance and verification complexity.

Module 5 Verifying CPU Microarchitectures

Identify verification targets, extend functional coverage and constraints, generate focused tests and work systematically towards coverage closure.

Module 6 riscv-dv Practical Exercises

Extend coverage and constraint models, generate and simulate tests, review results and consolidate the complete riscv-dv workflow through guided feedback.

Part 2 RISC-V CPU Verification

Apply the foundation to RISC-V ISA behaviour, software toolchains, CPU verification, architectural compliance and processor microarchitecture.

Module 7 Introduction to RISC-V

Learn RISC-V instruction formats, modular ISA design, privilege modes, the memory model and essential RISC-V assembly language.

Module 8 Writing and Running RISC-V Programs

Use RISC-V software toolchains and RARS to assemble, run and inspect assembler and C programs for the base ISA.

Module 9 RISC-V Programming Exercises

Write, convert and execute RISC-V assembler and C programs in RARS, then review results and implementation choices.

Module 10 Verifying CPU Integration in an SoC

Use software-driven testing on a mini-SoC to verify CPU integration and understand the role of compliance suites and benchmarks.

Module 11 RISC-V Verification and riscv-dv Tooling

Run riscv-dv, simulate generated tests, interpret pass and fail results, inspect functional coverage and modify selected constraints.

Module 12 riscv-dv CPU Verification Exercises

Complete the generation, simulation and coverage loop independently and review how stimulus and constraints influence verification evidence.

Module 13 RISC-V Architectural Compliance

Understand compliance requirements, run an example RISC-V compliance suite and interpret the resulting evidence.

Module 14 Advanced CPU Microarchitecture Concepts

Study registers and addressing, pipelining, hazards, out-of-order execution, branch prediction, register renaming, superscalar, vector and multicore processors.

Module 15 CPU Verification Review

Consolidate the principal RISC-V CPU verification concepts, practical workflows and their application to real engineering projects.

Module 16 Formal Verification Introduction

Understand where formal verification can complement simulation-based RISC-V CPU verification.

Part 3 RISC-V SoC Verification

Verify a RISC-V CPU inside an SoC using software-driven tests, assertions, functional coverage, debug and sign-off evidence.

Module 17 Introduction to SoC Verification

Understand the principal SoC verification tasks, the difference between IP- and SoC-level verification, and the metrics used for sign-off.

Module 18 Training SoC and Verification Environment

Review the training SoC architecture, testbench, simulation flow, assertions, self-checking tests and functional coverage model.

Module 19 Software-Driven SoC Verification Exercises

Run, modify and create RISC-V software tests, make them self-checking and add functional coverage for SoC behaviour.

Module 20 SoC Debug Exercises

Apply a structured bug-finding, triage and debug workflow to a known SoC defect and review the resulting evidence.

Module 21 Verifying a CPU Within an SoC

Plan verification for CPU integration, reset and boot, clocks and clock gating, power control, interrupts, system control and end-to-end use cases.

Module 22 SoC Verification and Sign-Off Exercises

Write and run SoC tests, collect coverage and verification metrics, and prepare a defensible SoC sign-off report.

Module 23 SoC Verification Review

Consolidate SoC verification strategy, practical exercises, debug lessons and application to live projects.

Module 24 Formal Verification for SoC

Understand how formal methods can support integration, control and sign-off objectives in RISC-V SoC verification.

The advanced series extends the standard programme for engineers working on processor microarchitecture, high-risk RISC-V CPU corner cases and complete subsystem or SoC verification. Each advanced part can be taken separately; the connected three-part bundle is Course +++.

Part 1++ Processor Microarchitectures and RISC-V ISA Advanced

Develop deeper architecture and ISA knowledge, then apply it to selected CVA6 block-level UVM verification. The approved outline groups this material by topic rather than assigning formal module numbers.

Microarchitecture models

Single-cycle, multi-cycle, pipelined and out-of-order execution, including hazards, forwarding, critical paths and performance trade-offs.

RISC-V M extension

Shift-and-add and Radix-4 Booth multiplication, restoring and Radix-4 division, and their hardware implications.

RISC-V A, F, C and B extensions

Atomic operations, floating-point arithmetic, compressed instruction decoding and the Bitmanip extension family.

RISC-V V vector extension

Vector registers, vl, SEW, LMUL, masking, tail policies and unit-stride, strided and indexed memory operations.

Custom RISC-V extensions

Extension naming and ordering, instruction encoding and opcode-space design with worked custom-instruction examples.

Out-of-order execution

Dynamic scheduling, Tomasulo algorithm, register renaming and speculative execution.

CVA6 block-level UVM verification

Design and interface reviews, verification planning, execution examples and practical exercises for the multiplier, serial integer divider and compressed decoder.

Part 2++ RISC-V CPU Verification Advanced

Target high-risk CPU corner cases using advanced instruction-stream generation, SystemVerilog and UVM constraints, functional coverage and Spike instruction-set-simulator reference checking.

Privileged architecture and CSR verification

Verify privilege transitions, CSR fields, legal and illegal accesses, side effects and cycle-by-cycle correctness.

Exceptions, interrupts and traps

Exercise trap entry and return, exception priority, interrupt timing and pipeline interactions.

Atomic instruction corner cases

Verify LR/SC and AMO behaviour, interference, failure modes and memory-system interaction.

Pipeline hazards and control flow

Target RAW and load-use hazards, forwarding, stalls, flushes and control-flow recovery.

Advanced instruction-stream generation

Use online and offline, cycle-accurate and retire-accurate generation modes to create focused CPU stimulus.

Constraints and functional coverage

Write realistic SystemVerilog/UVM-style constraints and coverage models, including cross-coverage for CSR, atomic and hazard scenarios.

UVM and Spike reference-model methodology

Use an ISG-driven instruction stream, monitor and scoreboard to compare DUT behaviour with the Spike golden reference model.

Part 3++ RISC-V SoC Verification Advanced

Apply advanced planning, formal, low-power, interconnect, memory and software-driven methods across fourteen connected SoC verification modules.

Module 1 Introduction to Advanced RISC-V SoC Verification

Establish the advanced subsystem and SoC verification scope, architecture risks and evidence expectations.

Module 2 Advanced SoC Planning Closure and Sign-Off

Build risk-based plans, measurable closure criteria and traceable sign-off evidence for a complex RISC-V SoC.

Module 3 Berkeley Out-of-Order Machine BOOM

Use an out-of-order RISC-V implementation to connect advanced microarchitecture behaviour with verification risk.

Module 4 ASIC Verification as a Resource-Limited Bug Search

Prioritise verification effort, scenarios and metrics where time, compute and engineering resources are constrained.

Module 5 Cross-Subsystem and Scenario-Driven Verification

Verify integration and end-to-end behaviour across interacting subsystems using realistic system scenarios.

Module 6 Formal Applications at SoC Level

Apply formal methods to selected SoC properties, control logic, corner cases and sign-off objectives.

Module 7 Formal Connectivity Verification

Prove critical connectivity and integration intent across interfaces, registers and subsystem boundaries.

Module 8 Power-Aware Verification and UPF Validation

Verify power intent, domains, isolation, retention and power-state behaviour using UPF-aware methods.

Module 9 Formal Verification for Low Power

Use formal techniques to verify UPF and low-power control behaviour that is difficult to cover exhaustively in simulation.

Module 10 Multi-Master AXI and Memory Interaction

Verify arbitration, ordering, backpressure and interaction between multiple bus masters and the memory system.

Module 11 Cache Coherency and Memory-System Verification

Target coherency states, races, ordering, sharing and cache-memory corner cases in RISC-V SoCs.

Module 12 Firmware OS Boot and Workload Verification

Use firmware-driven tests, operating-system boot and representative workloads to verify integrated SoC behaviour.

Module 13 Performance Stress and Resilience Verification

Measure performance, stress resources, inject faults and verify recovery and resilience under demanding workloads.

Module 14 Future Verification Trends

Review digital twins, in-field and runtime verification, and quantum and post-quantum hardware-verification considerations.

Depending on the selected pathway, participants will be able to:

• Explain the relationship between an ISA, CPU microarchitecture and verification architecture.
• Plan hierarchical verification across CPU blocks, the complete processor and a CPU-based SoC.
• Use instruction-stream generation and riscv-dv to create targeted RISC-V verification stimulus.
• Build and refine SystemVerilog/UVM constraints and functional coverage models.
• Run RISC-V assembler and C programs and use software-driven tests to verify CPU and SoC integration.
• Assess RISC-V architectural compliance and interpret compliance evidence.
• Verify CPU pipelines, CSRs, traps, atomics, hazards and selected microarchitectural features.
• Apply self-checking tests, assertions, reference models, debug and coverage closure techniques.
• Verify reset, boot, clocks, power, interrupts, AXI, cache coherency, firmware and operating-system workloads at SoC level.
• Prepare clear verification evidence and contribute to defensible CPU or SoC sign-off.

• Instructor-led teaching: Live online sessions establish the architecture, methodology and verification flow.
• Guided examples: Participants see workflows demonstrated before applying them independently.
• Practical exercises: Exercises cover code generation, simulation, constraints, coverage, compliance, software-driven SoC testing, debug and sign-off.
• Review and feedback: Joint sessions help participants consolidate techniques and relate them to project work.
• Flexible delivery: Current live and on-demand options, access periods, dates and prices are confirmed in the active course listing or by the Alpinum training team.