As RISC-V adoption expands, verification teams need engineers who can reason across CPU architecture, UVM-based CPU verification and software-driven SoC integration. Alpinum’s live online training develops those capabilities through structured teaching, quizzes, open-source workflows and practical exercises.
The programme is designed for engineers who are new to CPUs or CPU verification, including those verifying the integration of a CPU into a System-on-Chip (SoC). Participants build from CPU and RISC-V fundamentals to practical CPU- and SoC-level verification workflows they can relate to real engineering projects.
Course at a glance
| Delivery | Live online, instructor-led training |
| Structure | Three connected learning pathways |
| Practice | Quizzes, guided examples and independent exercises |
| Workflows | UVM, riscv-dv, RARS, coverage, compliance and software-driven SoC verification |
| Feedback | Classroom review, support and exercise feedback |
| Flexible scope | Full programme or a focused RISC-V pathway, subject to experience and agreed objectives |
Three-part programme structure
| Pathway | Coverage |
|---|---|
| Part 1 — CPU and RISC-V Basics | Build the architectural and verification foundation: ISAs, CPU microarchitecture, hierarchical verification, instruction-stream generation, functional coverage and riscv-dv exercises. |
| Part 2 — RISC-V CPU Verification | Apply the foundation to RISC-V: ISA concepts, assembler and C workflows, RARS, open-source UVM and riscv-dv workflows, architectural compliance and CPU microarchitecture. |
| Part 3 — RISC-V SoC Verification | Verify a RISC-V CPU inside an SoC using software-driven tests, self-checking methods, assertions, functional coverage, debug and sign-off exercises. |
Learning Outcomes
- Describe current best-practice CPU and CPU-based SoC design verification strategies.
- Explain the principal methodologies, tools and languages used in CPU and CPU-based SoC verification.
- Apply those methodologies, tools and languages to a basic RISC-V CPU design and an SoC design based on RISC-V.
- Analyse a real RISC-V CPU or SoC and propose an appropriate verification strategy.
- Discuss CPU and CPU-based SoC design verification topics confidently with engineering colleagues.
- Contribute more effectively to RISC-V CPU and SoC verification projects.
Who Should Attend?
- Graduate recruits and university placement students.
- Design or verification engineers who want to understand CPU and CPU-based SoC verification.
- Engineers moving into CPU verification, RISC-V verification or CPU integration.
- Engineering managers who need a working understanding of CPU and SoC verification strategies.
Prerequisites
Some experience with design verification and SystemVerilog using the Universal Verification Methodology (UVM) is beneficial. Contact Alpinum if you are unsure whether the full programme or a focused pathway is the best fit.
How the Training Works?
- Instructor-led teaching: Live online sessions connect CPU architecture, RISC-V concepts and design verification practice.
- Guided examples: Participants see workflows demonstrated before applying them independently.
- Practical exercises: Exercises cover code generation, simulation, coverage, compliance, software-driven SoC testing, debug and signoff.
- Review and feedback: Joint review sessions help participants consolidate techniques and relate them to project work.
