3-Part Live Online Training Programme

From Block-Level Safety Mechanisms to SoC-Level ISO 26262 Evidence

Build practical functional safety verification skills across RTL blocks, processors, safety clusters and complete SoCs.

This live instructor-led programme covers functional safety architectures, fault injection, ECC, parity, lockstep CPUs, diagnostic coverage, FMEDA, SystemVerilog Assertions, UVM, formal property verification and ISO 26262 safety evidence.

Training dates: 14–22 September 2026
Training time: 1:00–5:00 pm BST
Delivery: Live online via Microsoft Teams
Programme: 3 parts · 6 live sessions · 24 technical modules

Functional Safety Verification from RTL to SoC Sign-Off

Modern safety-critical semiconductor systems require more than functionally correct RTL. Safety mechanisms must detect faults, report errors, trigger appropriate reactions and generate measurable evidence that supports safety goals and compliance activities.

Alpinum’s Functional Safety Verification Training provides engineers with a structured path from fundamental safety concepts to full-stack verification and ISO 26262 evidence generation.

The programme begins with block-level safety mechanisms such as ECC, parity, CRC, watchdogs, protected state machines and safe-reset controllers. It then progresses to CPU and cluster-level architectures, including lockstep processing, cache protection, memory scrubbing, safety monitors and formal property verification.

The final part examines complete SoC safety architectures, Safety Management Units, Fault Collection Units, fault escalation, safe-state control, fault campaigns, FMEDA evidence and verification closure.

Participants will understand not only how safety mechanisms are designed, but how simulation, UVM, assertions, formal verification and fault injection work together to demonstrate that those mechanisms operate correctly. 

Course at a Glance

Programme Schedule

The technical progression is consistent across the curriculum: block-level safety verification in the first part, CPU and cluster-level safety in the second, and SoC-level evidence and compliance closure in the third.

What You Will Learn

By the end of the complete programme, participants will be able to:

• Understand functional safety lifecycles, ASIL levels and ISO 26262 verification expectations.
• Explain how hardware safety mechanisms detect, correct, report and respond to faults.
• Verify ECC, parity, CRC, watchdog, safe-reset and protected state-machine architectures.
• Develop structured fault injection environments for RTL and subsystem verification.
• Connect fault injection results and diagnostic coverage metrics to FMEDA evidence.
• Verify lockstep CPUs, cache ECC, memory scrubbing, TCM protection and register parity.
• Write and apply SystemVerilog Assertions for safety-critical properties.
• Understand where formal property verification complements simulation and UVM.
• Verify clock, voltage and thermal monitoring mechanisms.
• Plan CPU and SoC-level functional safety verification strategies.
• Verify fault aggregation, error routing, escalation and safe-state behaviour.
• Structure SoC-level fault campaigns for ISO 26262 evidence.
• Understand how simulation, UVM, formal verification and fault simulation contribute to a complete safety case.
• Define coverage closure and sign-off criteria for safety-critical semiconductor systems.

Who Should Attend

This training is designed for engineers and technical teams working in safety-critical semiconductor and embedded-system development, including:

• Functional safety engineers
• SoC and ASIC verification engineers
• RTL design engineers
• Automotive semiconductor engineers
• CPU and safety architects
• Design verification leads
• Embedded systems engineers
• UVM verification engineers
• Formal verification engineers
• Safety verification engineers
• FMEDA and diagnostic coverage teams
• ISO 26262 compliance teams
• Engineering managers responsible for safety-critical development

The programme is particularly relevant to teams developing automotive processors, safety controllers, embedded systems, safety islands, memory subsystems and safety-critical SoCs.

Three-Part Course Structure

Part 1: Safety Foundations and Block-Level Verification

Dates: 14–15 September 2026
Time: 1:00–5:00 pm BST
Sessions: 1–2

Part 1 introduces the safety lifecycle and establishes the connection between safety requirements, RTL safety mechanisms, fault models, verification results and FMEDA evidence.

Participants examine common block-level mechanisms and learn how their claimed safety behaviour can be tested, asserted, measured and documented.

Session 1: Fault Models, ECC and Error Detection

Module 1: Why Functional Safety Fails in Practice

Understand the ISO 26262 safety lifecycle, Automotive Safety Integrity Levels and the evidence required to support a safety argument.

The module examines the difference between specifying a safety mechanism and demonstrating through verification that it behaves correctly under realistic faults.

Module 2: ECC: From Algorithm to RTL and Fault Injection

Explore Hamming codes, SECDED behaviour and the implementation of ECC generation and checking in SystemVerilog.

Participants examine how to inject single-bit and double-bit errors, verify correction and detection behaviour, and measure results against diagnostic coverage targets.

Module 3: Parity and CRC: Detection Without Correction

Understand how parity and CRC mechanisms detect data corruption and where each technique is appropriate.

Verification topics include directed and constrained-random fault injection, SVA-based error detection properties and safety coverage closure.

Module 4: Watchdog Architectures and FSM Protection

Examine window watchdogs, question-and-answer watchdogs, protected state machines, illegal-state detection and safe-state encoding.

Participants learn how assertions and formal verification can check timeout behaviour, illegal-state handling and safe-reset responses.

The first session therefore moves from safety lifecycle fundamentals to ECC, parity, CRC, watchdog and FSM protection verification.

Session 2: Reset, FMEDA and Fault Infrastructure

Module 5: Safe Reset Controllers and Error Reporting

Study safe-reset sequencing, cold and warm reset paths, error status registers, masking, clearing and fault reporting to higher-level safety managers.

Verification covers reset completeness, fault propagation and sticky versus clearable error flags.

Module 6: ASIL Decomposition and FMEDA Fundamentals

Understand ASIL decomposition, failure modes, failure rates, diagnostic coverage, safe failure fraction and the role of FMEDA in a semiconductor safety programme.

Participants learn how verification evidence can be mapped to individual FMEDA line items.

Module 7: Fault Injection Infrastructure

Examine stuck-at faults, single-event upsets, error injector modules and the difference between simulation fault injection and silicon-level fault injection.

The module also introduces UVM fault sequences, coverage groups and regression plans linked to FMEDA targets.

Module 8: Block-Level Safety Verification Report

Learn how to structure a block-level safety verification plan and report.

The report should identify the verified safety mechanisms, fault coverage results, limitations, residual risks and additional work needed before sign-off.

Session 2 connects reset and error-reporting behaviour with ASIL decomposition, FMEDA and structured fault injection.

Part 2: CPU/Cluster-Level Safety

Dates: 16–17 September 2026
Time: 1:00–5:00 pm BST
Sessions: 3–4

Part 2 progresses from individual safety IP to CPU and cluster-level architectures.

Participants learn how multiple protection mechanisms interact and how simulation, UVM, assertions and formal property verification contribute to CPU-level diagnostic coverage.

Session 3: Lockstep, Cache ECC and CPU Safety Verification

Module 1: From Block to CPU: Lockstep Architecture

Understand dual-core lockstep architectures, cycle-accurate comparison and the distinction between tight and loose lockstep implementations.

Verification includes fault injection, comparator timing, comparison correctness and formal coverage.

Module 2: Cache ECC and Memory Scrubbing

Explore cache write encoding, read checking, single-bit correction, double-bit detection and background memory scrubbing.

Participants examine a UVM verification architecture for cache ECC, including agents, monitors, scoreboards and fault injection sequences.

Module 3: TCM Protection and Register Parity

Study Tightly Coupled Memory protection, register-file parity, fault detection latency and error handling.

The module explains how constrained-random verification and functional coverage extend beyond directed fault testing.

Module 4: SVA Safety Assertions at the CPU Level

Learn assertion patterns for lockstep comparison, watchdog timing, ECC error handling and illegal CPU safety states.

Participants examine how concurrent assertions can be bound to a design and how assertion coverage contributes to safety evidence.

These modules cover lockstep architecture, cache ECC, TCM protection, register parity and CPU-level assertions.

Session 4: Formal Safety, Monitors and FMEDA Closure

Module 5: Formal Property Verification of Safety Mechanisms

Understand which safety properties can be proven formally and which behaviours still require simulation.

Participants learn how assume, assert and cover properties describe safety intent and how formal results can support diagnostic coverage claims.

Module 6: Clock, Voltage and Thermal Monitors

Explore missing-clock detection, PLL lock monitoring, brownout and overvoltage detection, thermal monitoring and shutdown sequencing.

Verification covers detection windows, response latency, threshold behaviour and the use of both UVM and formal methods.

Module 7: CPU-Level FMEDA and Diagnostic Coverage

Learn how diagnostic contributions from lockstep processing, cache ECC, register parity, watchdogs and monitors combine at the CPU level.

Participants examine how regression results map to failure modes and ASIL targets.

Module 8: Safe Boot and CPU-Level Safety Integration

Examine safe boot architecture, ROM control, signature verification, boot diagnostics and hardware-supported chains of trust.

The module connects safe boot, CPU safety mechanisms, simulation and formal verification into an integrated safety strategy.

Session 4 combines formal property verification, safety monitoring, CPU-level FMEDA and safe-boot integration.

Part 3: SoC-Level Full DV and ISO 26262 Evidence

Dates: 21–22 September 2026
Time: 1:00–5:00 pm BST
Sessions: 5–6

Part 3 brings the complete verification workflow together at SoC level.

Participants examine how faults move from individual IP blocks through collection, classification and routing logic to interrupt, reset or safe-state reactions.

The final session focuses on fault campaigns, FMEDA evidence, verification-layer closure and construction of a full-stack safety argument.

Session 5: SoC Safety Architecture and Fault Management

Module 1: SoC Safety Architecture and Verification Strategy

Understand how the Safety Management Unit, Fault Collection Unit, error router, diagnostic controller, safe-state controller and software drivers interact across an SoC.

The verification focus includes safety DV planning, regression management, fault campaign strategy and ASIL-oriented coverage closure.

Module 2: Safety Management Unit: Full Design Verification

Study fault aggregation, classification, reaction mapping and software alarm interfaces.

Participants examine scoreboard-based fault-routing verification, full fault-injection regressions and formal connectivity checks.

Module 3: Fault Collection Unit and Error Routing

Explore source-level fault signals, masking, aggregation, priority encoding and routing to system-level safety mechanisms.

Verification includes simultaneous fault injection, prioritisation, escalation and correct delivery to the Safety Management Unit.

Module 4: Safe-State Controller and Error Escalation

Understand safe-state entry conditions, hardened control logic, safe-state outputs and controlled recovery sequences.

Formal properties are used to demonstrate that fatal faults trigger safe-state entry within the required time and that recovery cannot occur unintentionally.

Session 5 focuses on SoC safety architecture, fault management, error routing and safe-state escalation.

Session 6: Fault Campaigns, FMEDA Evidence and Compliance Closure

Module 5: Fault Campaigns: Stuck-At, SEU, Clock Failure and Bus Error

Examine SoC-level fault models, including stuck-at faults, single-event upsets, missing clocks, spurious clock edges and bus protocol errors.

Participants learn how to construct a traceable fault campaign linked to diagnostic mechanisms and FMEDA targets.

Module 6: FMEDA Evidence Generation from Simulation

Understand failure mode enumeration, diagnostic coverage, safe failure fraction and residual fault probability at SoC level.

The module demonstrates how fault injection results can be converted into structured FMEDA and safety-case evidence.

Module 7: Secure and Safe Boot: End to End

Follow the complete boot sequence from power-on reset through ROM, bootloader and operating system.

Verification covers interactions between boot control, secure processing, key management, lifecycle control and fault handling at each stage.

Module 8: Verification Layer Closure and Full-Stack Safety Case

Understand what is demonstrated by directed fault injection, constrained-random UVM, assertions, formal property verification and fault simulation.

Participants learn how the different verification layers combine to support diagnostic coverage, FMEDA evidence, safe-state behaviour and ISO 26262 sign-off.

The final session connects SoC fault campaigns to FMEDA evidence and a complete safety case.

Standard Session Format

Each four-hour live session follows a structured format combining technical instruction, practical demonstrations and knowledge checks.

The curriculum allocates four 45-minute modules, two demonstrations, two quizzes and a short break within each four-hour session.

Verification Methods Covered

The programme brings together multiple verification techniques rather than treating any single method as sufficient for safety sign-off.

Directed Fault Injection

Use targeted faults to verify known safety mechanisms, error responses and recovery behaviour.

Constrained-Random UVM Verification

Generate broader fault and operational scenarios while measuring functional and fault coverage.

SystemVerilog Assertions

Express timing, detection, escalation and safe-state requirements as executable properties.

Formal Property Verification

Prove critical safety properties and explore behaviours that may be difficult to reach through simulation alone.

Fault Simulation

Execute structured campaigns across larger fault lists and extract diagnostic coverage evidence.

FMEDA Evidence Mapping

Connect verification results to failure modes, diagnostic mechanisms and claimed safety metrics.

Training Format

• Live online instructor-led training
• Six four-hour technical sessions
• Two consecutive sessions within each part
• Technical presentations and guided explanations
• Practical demonstrations and walkthroughs
• Knowledge checks during each session
• Real-world safety verification workflows
• RTL, CPU, cluster and SoC-level examples
• UVM, SVA, formal verification and fault injection coverage
• Questions and technical discussion with the instructor

Key Benefits

By attending the programme, engineering teams can:

• Develop a consistent understanding of functional safety verification across design levels.
• Connect ISO 26262 safety requirements to practical RTL and DV activities.
• Improve verification planning for safety mechanisms and fault responses.
• Understand how diagnostic coverage claims should be supported by evidence.
• Combine UVM, SVA, formal verification and fault injection more effectively.
• Identify gaps between specified safety behaviour and verified behaviour.
• Improve traceability between fault campaigns, FMEDA and the safety case.
• Establish clearer CPU and SoC-level safety sign-off criteria.
• Build a more defensible end-to-end safety verification strategy.

Recommended Background

The programme is most suitable for participants with a basic understanding of digital hardware, RTL design or design verification.

Familiarity with SystemVerilog, UVM, assertions or formal verification will be useful, but participants do not need to be experts in every method covered.

Functional Safety Verification and ISO 26262

ISO 26262 requires safety activities to be planned, performed and supported by appropriate evidence throughout the automotive product lifecycle.

For semiconductor teams, this includes demonstrating that safety mechanisms detect relevant faults, respond within the required time and achieve the diagnostic coverage claimed within safety analyses.

Functional safety verification therefore connects multiple engineering activities:

• Safety requirements
• RTL architecture
• Safety mechanisms
• Verification planning
• Fault modelling
• Fault injection
• Diagnostic coverage
• FMEDA
• Verification reports
• Safety-case evidence
• Sign-off and compliance closure

This programme explains how those activities connect from an individual RTL block to a complete safety-critical SoC.

Related Alpinum Training

Teams may also be interested in:

Hardware and Software Security Verification Training

Explore secure boot, silicon roots of trust, CPU security, information-flow verification and system-level security assurance.

Formal Verification Training

Build practical formal verification skills covering assertions, property development, proof strategies and formal sign-off workflows.

Low Power Verification Training

Learn how to verify power intent, isolation, retention, power-state transitions and low-power behaviour.

FAQs

Register for Functional Safety Verification Training

Develop an end-to-end understanding of functional safety verification across RTL blocks, processors, safety clusters and complete SoCs.

Join the full three-part programme to explore safety mechanisms, fault injection, UVM, assertions, formal property verification, diagnostic coverage, FMEDA evidence and ISO 26262 verification closure.

Dates: 14–22 September 2026
Time: 1:00–5:00 pm BST
Delivery: Live online via Microsoft Teams

Student discount available

Eligible university students can apply for discounted access through Alpinum’s University Student Access Programme.