The Design Verification (DV) course (delivered by Dr. Mike Bartley) met our main objective which was to upskill our graduate and junior verification engineers to have the knowledge and understanding of verification to start supporting projects in the shortest time possible whilst minimising initial training and supervision time from our senior engineers.

The course completely covered the principles and background of DV to give a good foundation for the application of current best practice in constrained random stimulus generation, automated checkers and both code and functional coverage. All of this was bought together by the practical application of these techniques to an extensive set of examples and exercise that culminated in a full SV and UVM test bench. The course also compared and contrasted simulation and formal approaches to verification, allowing for a good understanding where each may be best deployed. Additionally, the course introduced important topics that might influence DV in the future, such as the application of AI/ML.

The course covers both IP, integration and SoC verification with the latter using an SoC running C-based tests running on an embedded CPU. A particular IP block is followed through the hierarchy and this enabled students to put each level of verification into context and understand the whole process to better appreciate the complete process from verification panning to signoff, and the activities and signoff criteria used at each level.

Course understanding was helped with the extensive set of examples and exercises mentioned above. In addition, the course uses short quizzes in class to give a quick check on student understanding of a concept. These also prompted discussion which helps the interaction in online delivery. The course also provides continuously available online tests with immediate, automated feedback on student answers to help consolidate understanding. These are delivered using the Moodle platform which also allowed Dr. Bartley to track individual student progress and give individualised feedback. Dr. Bartley also kept us fully informed on course attendance.

One of the key benefits was he flexible delivery and timing of the course which not only allowed graduate participants to continue working on their own assigned projects during the training but also some senior engineers to participate to brush up their skills and also have first-hand feedback of how the junior engineers are progressing through the course. We did not have to assign internal senior engineers to support the upskilling of these engineers.

The course was delivered by Dr. Bartley, a very senior presenter with over 30 years’ experience in DV who is still very active in the industry running large verification teams; organising, attending and speaking at conferences; providing DV training; helping companies to improve verification strategies, processes and efficiency; as well as being active in research. He was able to provide valuable insights into the practicalities of verifying real designs and was very responsive to participant questions, taking time outside of the online sessions to give individual support.

After each delivery of the course, Dr. Bartley took extensive feedback from all participants which get incorporated into the next delivery. We continue to put students on this course who benefit from this continuous improvement. We have also used a variation of the course for analog/mixed-signal verification and a new course on CPU verification. We continue to be impressed by the quality of both content and delivery.

– Senior Director of Verification, Infineon Technologies