The Design Verification course (delivered by TechWorks Academy) met our main objective which was to upskill our graduate engineers to have the knowledge and understanding of the application of VHDL and OSVVM in verification environments, the course also covered SV and UVM. Course understanding was helped with the extensive set of examples and exercises which allowed the participants to progress from initially simple, to complex design and test benches – which included debug and fix.

The flexible delivery and timing of the course allowed participants to continue working on their own assigned projects during the training. We did not have to assign internal senior engineers to support the upskilling of these engineers.

The course was delivered by a very senior presenter with over 30 years’ experience in Design Verification. He was able to provide valuable insights into the practicalities of verifying real designs and was very responsive to participant questions, taking time outside of the online sessions to give individual support.

After the 1st run and full delivery of the course, the organiser took extensive feedback from all participants which has now been incorporated into the next course. The next course will start on February 7th and we have already registered 8 participants for this.

– Pete Leonard, Electronics Design Manager, Group Engineering, Renishaw