Build and verify power-aware mixed-signal systems using UPF, SystemVerilog, Verilog-AMS, SPICE and UVM methodologies.
Live, instructor-led AMS co-simulation training for design verification, mixed-signal and low-power engineers. Develop practical skills in AMS and UPF integration, power-aware mixed-signal verification, voltage-domain boundary management, PA-UVM sequencing and advanced debugging.
Build Practical Power-Aware AMS Verification Skills
Modern mixed-signal verification increasingly requires engineers to consider three interacting areas at the same time: analogue behaviour, digital control and power intent. A mixed-signal block may behave correctly in isolation yet encounter problems when power domains switch state, supplies change, digital control sequences interact with analogue behaviour, or signals cross boundaries between different voltage domains. Power-aware AMS verification therefore requires more than conventional digital simulation or standalone analogue analysis. Engineers need to understand how AMS co-simulation, Unified Power Format (UPF), mixed-signal modelling, UVM sequencing and debug workflows fit together.
This training develops that capability through a focused progression from AMS and UPF fundamentals to power-aware boundary management and PA-UVM debugging. Participants explore how power domains and Power State Tables influence verification, how isolation and level shifting affect mixed-signal boundaries, how UVM can support power-aware sequencing, and how debugging techniques can be applied to X-corruption and simulation convergence problems.
Course Overview
The AMS Co-Simulation (Power-Aware / UPF) Training programme is designed for engineers working where low-power architecture meets analogue and digital verification. Across three instructor-led sessions, the course introduces the foundations of AMS and UPF integration before progressing into multi-voltage boundary management and practical PA-UVM verification.
The programme covers SystemVerilog, Verilog-AMS, IEEE 1801 UPF concepts, SPICE modelling, power domains, Power State Tables, connect modules, isolation strategies, level shifting, UVM power sequencing and mixed-signal debugging. A Power-Aware SAR ADC Verification Lab brings the concepts together in a representative mixed-signal verification exercise.
For current course availability and registration, visit the Alpinum Training page.
Course at a glance
| Area | Details |
|---|---|
| Delivery | Live, instructor-led online training |
| Structure | 3 progressive, instructor-led sessions |
| Duration | 3 × 2-hour sessions · 6 hours total |
| Core focus | AMS co-simulation and power-aware mixed-signal verification |
| Power intent | Unified Power Format (UPF) / IEEE 1801 |
| Languages and methodologies | SystemVerilog, Verilog-AMS, UVM and UPF |
| Simulation concepts | SPICE modelling and AMS co-simulation |
| Boundary verification | Connect modules, isolation, level shifting and multi-voltage domains |
| Debug focus | PA-UVM, X-corruption and convergence analysis |
| Practical exercise | Power-Aware SAR ADC Verification Lab |
What You Will Learn
By completing the AMS Co-Simulation Power-Aware / UPF training, participants will develop practical understanding of how power intent can be incorporated into mixed-signal verification environments.
You will learn how to:
- Understand the relationship between AMS co-simulation and UPF-based power intent
- Work with power domains and Power State Tables in power-aware verification flows
- Configure power-aware mixed-signal verification environments
- Understand the role of SystemVerilog, Verilog-AMS and SPICE within AMS co-simulation
- Apply connect-module and threshold-mapping concepts at mixed-signal boundaries
- Understand isolation strategies across powered and unpowered domains
- Integrate level shifters across different voltage domains
- Manage verification considerations across multiple voltage domains
- Integrate UVM concepts with power-aware AMS verification
- Develop power-aware UVM sequencing
- Analyse power-aware mixed-signal waveforms
- Investigate X-corruption and simulation convergence problems
- Apply structured mixed-signal debugging methodologies
- Connect these techniques through a practical Power-Aware SAR ADC verification exercise
Who Should Attend?
This training is designed for engineers and technical professionals involved in low-power, analogue, digital or mixed-signal semiconductor verification.
It is particularly relevant for:
- Design Verification Engineers working with complex SoCs or mixed-signal subsystems
- AMS / Mixed-Signal Engineers who need to incorporate explicit power intent into verification
- Low-Power Verification Engineers working with UPF and multi-voltage architectures
- UVM Verification Engineers extending digital verification methodology into power-aware AMS environments
- Verification Leads and Architects responsible for mixed-signal verification methodology and integration
If you are unsure which AMS training course best matches your experience or project requirements, use the Training page to review the available learning paths.
Looking for the next course date?
Upcoming AMS training dates and current registration options are maintained on our main Training page.
Why Power-Aware AMS Verification Matters
Mixed-signal verification becomes particularly challenging when an analogue block does not operate under one fixed power condition. Modern semiconductor systems may contain multiple power domains, different voltage levels and operating states that change during system operation. Digital control logic may initiate shutdown, start-up or other power transitions while analogue blocks and their interfaces respond continuously.
Verification must therefore account for both the behaviour of the mixed-signal system and the power state in which that behaviour occurs. This is where UPF and AMS co-simulation become important. UPF provides a standardised way of expressing power intent, while AMS simulation provides the environment needed to analyse interactions between digital and analogue behaviour. When UVM-based verification is added, engineers can build more structured approaches to stimulus, sequencing and debug around these interactions.
The engineering challenge is not simply whether an individual block functions. It is whether analogue behaviour, digital control and power intent remain consistent as the system moves between operating conditions. Alpinum’s wider AMS engineering work similarly treats mixed-signal verification as an interaction problem across analogue behaviour, digital control, modelling strategy and power-aware co-simulation.
Course Structure
The programme is organised as three progressive sessions. Each session builds on the previous stage so that participants move from fundamental concepts into practical power-boundary management and PA-UVM debugging.
Session 1: AMS & UPF Fundamentals
Build the foundation for power-aware mixed-signal co-simulation
The first session introduces the core concepts needed to understand how AMS simulation and UPF-based power intent work together.
Participants establish the relationship between SystemVerilog, Verilog-AMS, SPICE-based modelling and power-aware verification before examining the basic UPF structures used to describe power domains and system power states.
Topics covered
- SystemVerilog and Verilog-AMS fundamentals
- IEEE 1801 / UPF fundamentals
- Power domains
- Power State Tables
- SPICE modelling basics
- VCS and PrimeSim synchronisation
Practical focus
Understand the technical foundations needed to construct and reason about a power-aware AMS co-simulation environment.
Session 2: Power-Aware Boundary Management
Verify behaviour across voltage and power-domain boundaries
Mixed-signal verification becomes more complex when signals move between domains with different voltage or power states.
The second session focuses on the mechanisms and verification considerations involved at these boundaries.
Participants examine connect-module behaviour, threshold mapping, isolation strategies, level shifting and multi-voltage domain management before considering the associated compilation flow.
Topics covered
- Connect modules
- Threshold mapping
- Isolation cell strategies
- Level shifter integration
- Multi-voltage domain management
- VCS-NLP compilation flow
Practical focus
Develop a clearer understanding of how signals and verification assumptions must be managed as they cross analogue, digital, voltage and power-domain boundaries.
Session 3: PA-UVM & Debug
Apply UVM and structured debugging to power-aware AMS environments
The final session moves from environment configuration to verification sequencing and debug.
Participants explore how UVM can be applied in a power-aware AMS context, how power-aware waveforms can support analysis, and how specialist debugging approaches can help investigate complex mixed-signal failures.
Topics covered
- UVM power sequencing
- Power-aware waveform generation
- Verdi PA and AMS debugging
- X-corruption analysis
- Convergence analysis
- Mixed-signal debugging methodologies
Practical focus
Build a more repeatable approach to PA-UVM verification and debugging across power-aware mixed-signal systems.
Practical Exercise
Power-Aware SAR ADC Verification Lab
The course includes a Power-Aware SAR ADC Verification Lab that brings together concepts introduced across the three sessions.
The exercise provides a representative mixed-signal context in which participants can consider the interaction between power intent, analogue behaviour, digital control, verification sequencing and debugging.
Rather than treating UPF, AMS simulation and UVM as independent topics, the exercise helps connect them within a single verification workflow.
The practical focus reinforces the central objective of the programme: understanding how power-aware verification techniques can be applied where analogue and digital behaviour meet.
Key Power-Aware AMS Concepts Covered
AMS Co-Simulation
AMS co-simulation allows analogue and digital behaviour to be evaluated within a coordinated verification environment. This is particularly important where digitally controlled functionality interacts with continuous-time analogue behaviour.
The course introduces the mixed-signal simulation concepts needed to understand these interactions before applying power intent.
Unified Power Format – UPF / IEEE 1801
UPF is used to represent power intent separately from the functional RTL description.
Within this training, participants are introduced to UPF fundamentals in the context of AMS verification, including power domains and Power State Tables.
The emphasis is on understanding how power intent affects verification behaviour rather than treating UPF as an isolated language topic.
Power Domains and Power State Tables
Power domains identify regions of a design that can operate under different power conditions.
Power State Tables help describe valid combinations of supply and operating states.
For mixed-signal verification, these concepts become important because analogue behaviour and digital control must remain correctly coordinated while the system changes power state.
Isolation
Isolation strategies prevent unintended values from propagating from a domain whose power state makes its output unreliable.
The course explores isolation in the context of power-aware mixed-signal boundary management.
Level Shifting
Signals moving between different voltage domains may require level shifting.
Understanding how these boundaries are represented and verified is an important part of multi-voltage AMS verification.
Connect Modules and Threshold Mapping
Mixed-signal environments often require explicit handling of the interface between analogue and digital representations.
Connect modules and threshold mapping help define how those domains communicate, making boundary configuration an important part of AMS verification.
PA-UVM
Power-aware UVM extends structured verification thinking into environments where power sequencing and mixed-signal behaviour must be considered alongside conventional stimulus and checking.
The course introduces UVM power sequencing as part of the progression from environment setup to verification execution.
X-Corruption and Convergence Debug
Power transitions can introduce challenging simulation symptoms.
The programme includes approaches to analysing X-corruption, convergence behaviour and mixed-signal debugging, helping engineers understand how to investigate failures rather than simply observing that a simulation has failed.
From AMS Fundamentals to Power-Aware Debug
The structure of this training is deliberately progressive.
1. Establish the mixed-signal and power-intent foundation
Understand AMS co-simulation, modelling concepts, UPF, power domains and Power State Tables.
2. Manage the boundaries
Explore how connect modules, thresholds, isolation, level shifting and multi-voltage domains affect verification.
3. Verify and debug the complete environment
Apply UVM power sequencing and power-aware debug techniques to investigate complex AMS behaviour.
This progression helps connect concepts that are often learned separately into a more coherent power-aware mixed-signal verification workflow.
How each module works
Training Format
Live Online Training
The programme is delivered as instructor-led online technical training.
Three Progressive Sessions
Three focused sessions develop the subject from AMS and UPF foundations through power-boundary management to PA-UVM and debug.
Six Hours Total
The programme provides six hours of focused technical instruction.
Practical Engineering Context
Technical concepts are connected to verification workflows and a Power-Aware SAR ADC exercise rather than being presented only as isolated definitions.
Interactive Learning
The live delivery format supports technical discussion and questions around the concepts covered during the programme.
Key Benefits
By completing this training, engineers can strengthen their understanding of the verification challenges created when power intent and mixed-signal behaviour interact.
Key benefits include:
- Build practical understanding of UPF and AMS integration
- Develop greater confidence with power domains and Power State Tables
- Understand mixed-signal power-boundary verification
- Improve understanding of isolation and level-shifting strategies
- Connect multi-voltage domain concepts with AMS co-simulation
- Understand how UVM power sequencing fits into power-aware verification
- Develop stronger approaches to X-corruption and convergence debugging
- Connect SystemVerilog, Verilog-AMS, SPICE, UPF and UVM concepts within one learning path
- Apply the learning through a Power-Aware SAR ADC verification exercise
Related AMS Engineering Expertise
Training is supported by Alpinum’s wider work across analog and mixed-signal design, modelling, simulation and verification. Alpinum’s AMS capability includes mixed-signal verification planning, behavioural modelling, RNM/UVM-based flows and power-aware AMS co-simulation, providing useful technical context around the training portfolio.
For engineering teams looking for project support rather than training:
Frequently Asked Questions
Build Practical Power-Aware AMS Verification Capability
Develop a stronger understanding of how AMS co-simulation, UPF, multi-voltage boundaries, PA-UVM and mixed-signal debugging work together in modern semiconductor verification environments.
Progress from AMS and UPF fundamentals through power-aware boundary management to structured UVM sequencing and debug.
