AI-Era SoCs Push Verification Towards Top-Level Use-Case Tests
Harry Foster’s September 2026 analysis of the Siemens EDA and [...]
Preparing for a Career Change or New Role in Design Verification? Build Skills on Your Timeline
A move into design verification does not always begin immediately [...]
Directed Testing vs Constrained-Random UVM: A Practical Migration Path for Verification Engineers
Directed tests remain valuable because they reproduce known scenarios precisely, [...]
When Formal Proofs Do Not Converge: Diagnosing Unproven Properties, Bounded Results and Proof Complexity
When a formal property neither produces a valid counterexample nor [...]
UVM Scoreboard vs Assertions: Where Reference Models Fit
A self-checking verification environment needs more than stimulus. It needs [...]
When a Formal Proof Passes for the Wrong Reason: Vacuity, Over-Constraint and Unreachable Properties
A formal tool reports PROVEN. Every assertion on the dashboard [...]
X-Propagation in RTL: How Formal Verification Finds Reset and Unknown-State Bugs
An RTL simulation can finish reset, run thousands of tests [...]
IP, Subsystem and SoC Verification: What Changes in Stimulus, Checking, Coverage and Sign-Off?
Verifying an IP block, a subsystem and a complete [...]
From Simulation to Formal Proof: A Practical Learning Path for Verification Engineers
Simulation is the starting point for most verification engineers. Engineers [...]
