What Is UVM in Design Verification? Universal Verification Methodology Explained
UVM stands for Universal Verification Methodology. It is a SystemVerilog-based [...]
Learning by Doing in Semiconductor Verification: Why Practical Training Builds Better Engineers
True mastery rarely comes from passive observation. Engineers do not [...]
The Road to Chiplet Scalability: Why Verification and Test Must Scale Too
What the EE Times Chiplets Virtual Conference Signals for Multi-Die [...]
AMS Verification Challenges: Why Mixed-Signal Programmes Still Fail Late
Modern semiconductor programmes rarely fail because a single block is [...]
Published in Electronics World: The Growing Role of Formal Verification in RISC-V Design
Electronic systems are becoming harder to verify with simulation alone. [...]
Using Formal Verification for ISO 26262 Safety Compliance in Automotive Semiconductor Design
Introduction Automotive semiconductor design operates under sustained pressure to ensure [...]
Formal Security Verification in SoC Design: Preventing Data Leakage and Unauthorised Access at Chip Level
Introduction Modern SoCs operate across multiple trust levels. They expose [...]
CPU Processor Verification in the AI Era
Lessons from DVClub Bristol January 2026 for System-Level Confidence Introduction [...]
The AHAA Model: Structuring Formal Verification
Introduction Formal verification succeeds when teams align tools, properties, and [...]
