Huawei Ascend 960 AI Chips: Why SuperPoD Scale Changes Verification
At HUAWEI CONNECT 2026 in Shanghai on 17 September, the [...]
Coverage-Guided AI Testbench Generation: What CovR Means for Sign-Off
Coverage-guided AI testbench generation turns testbench writing from a one-shot [...]
Published in Electronics World: Agentic AI Is Changing Design Verification
Mike Bartley, CEO of Alpinum Consulting, continues his Silicon Systems [...]
Alpinum Brings Evidence-Led AI Engineering Training to India
Alpinum Consulting is bringing its evidence-led approach to AI engineering [...]
Architect Labs Redwood: Can AI Really Design and Verify a Chip in Two Weeks?
Architect Labs says its AI system designed and verified Redwood, [...]
Google-Marvell AI Chip Deal: What the $12.2bn Warrant Means for Custom Silicon, TPUs and Verification
Marvell disclosed on 19 August 2026 that it had expanded [...]
Can AI-Generated UVM Testbenches Detect Controlled RTL Changes? New AlpinumDV Mutation Results
Generating a UVM testbench with AI is one challenge. Evaluating [...]
AI-Assisted Verification: Why Sign-Off Still Depends on Engineering Intent
Mike Bartley, CEO of Alpinum Consulting, continues his Silicon Systems [...]
Anthropic’s AI Chip Plan: What Claude Custom Silicon Means for Design, Verification and AI Inference
Anthropic has confirmed that it is building an internal team [...]
