Published in Electronics World: Building Trustworthy AI Workflows for Semiconductor Engineering
Mike Bartley, CEO of Alpinum Consulting, continues his Silicon [...]
GPT-Synopsys and the Future of Chip Design: Why AI Outputs Still Need Verification and Sign-Off
Introduction On 30 September 2026, OpenAI and Synopsys announced GPT-Synopsys, [...]
Cadence ChipStack AI Super Agent: What RTL Generation Changes for Verification and Sign-Off
Cadence has expanded its ChipStack AI Super Agent with an [...]
Huawei Ascend 960 AI Chips: Why SuperPoD Scale Changes Verification
At HUAWEI CONNECT 2026 in Shanghai on 17 September, the [...]
Coverage-Guided AI Testbench Generation: What CovR Means for Sign-Off
Coverage-guided AI testbench generation turns testbench writing from a [...]
Published in Electronics World: Agentic AI Is Changing Design Verification
Mike Bartley, CEO of Alpinum Consulting, continues his Silicon Systems [...]
Alpinum Brings Evidence-Led AI Engineering Training to India
Alpinum Consulting is bringing its evidence-led approach to AI engineering [...]
Architect Labs Redwood: Can AI Really Design and Verify a Chip in Two Weeks?
Architect Labs says its AI system designed and verified Redwood, [...]
Google-Marvell AI Chip Deal: What the $12.2bn Warrant Means for Custom Silicon, TPUs and Verification
Marvell disclosed on 19 August 2026 that it had expanded [...]
