Mike Bartley, CEO of Alpinum Consulting, continues his Silicon Systems Design column in the September 2026 edition of Electronics World with:
“Agentic AI is changing design verification”
Artificial intelligence in design verification is moving beyond isolated assistance.
Verification teams have already been exploring AI for activities such as code generation, assertion support, regression analysis, coverage review, log summarisation and debug assistance. The next development is more significant: AI systems that can pursue a verification objective across multiple steps rather than responding to one engineering request at a time.
A verification agent may be able to interpret an objective, plan an activity, invoke an engineering tool, analyse the result and use that evidence to determine what should happen next.
That creates an important question for semiconductor verification teams:
How much autonomy can an AI verification agent safely have, and where must engineering control remain explicit?
That is the focus of Mike’s latest Electronics World column.
Read the full September 2026 Electronics World column
This new article continues the discussion from Mike’s July/August Electronics World column on AI-assisted verification, engineering intent and sign-off responsibility. The previous article established that AI can accelerate verification activity but cannot take ownership of sign-off. The September column moves the argument forward by examining what happens when AI begins to operate across the verification workflow rather than simply assisting individual tasks.
From AI assistance to verification agents
Most verification environments are already highly automated.
Regression systems schedule tests. Simulators execute verification environments. Formal engines explore state spaces. Coverage tools collect evidence. Debug environments help engineers investigate failures.
Agentic AI introduces a different layer of automation.
Instead of being asked to produce one test or summarise one log, an AI agent can potentially work towards an engineering objective across a sequence of activities.
For example, an agent investigating an uncovered design behaviour could identify the relevant requirement, examine existing tests and assertions, propose new stimulus or properties, invoke simulation or formal analysis, inspect the resulting evidence and recommend the next verification action.
The underlying EDA tools still perform the engineering execution. The important change is that AI begins to coordinate the loop between those tools and activities.
This distinction separates a verification agent from a conventional AI copilot.
A copilot primarily assists an engineer with a task. An agent can increasingly participate in deciding how a defined task should progress.
Why verification agents need a different standard
Design verification cannot judge an autonomous system only by whether it completes its assigned workflow.
A generated test may execute successfully without exercising the behaviour that matters most. A formal property can prove successfully while encoding the wrong interpretation of a requirement. Coverage can increase without materially reducing functional risk.
Similarly, a passing regression does not prove that a design is correct. It demonstrates that no failure was detected within the behaviours exercised under the conditions of that regression.
This makes verification different from many general software-agent use cases.
The engineering question is not simply:
Did the agent complete the task?
It is:
Did the resulting activity produce defensible verification evidence against the intended behaviour of the design?
That distinction is central to using agentic AI responsibly in semiconductor development.
Engineering context becomes part of the agentic workflow
For a verification agent to act usefully, it requires more than RTL and access to an AI model.
It may need to understand specifications, verification objectives, testbench architecture, assertions, assumptions, coverage models, reference models, approved waivers and sign-off criteria.
That context must also remain current.
An agent acting on an obsolete verification plan or an ambiguous requirement may perform its workflow correctly while reaching the wrong engineering conclusion.
This makes context itself a controlled verification asset.
Ownership, versioning and traceability become increasingly important because engineers need to understand which requirement, RTL revision, constraint set, verification plan and evidence contributed to an AI-assisted action.
Established methodologies such as UVM and Portable Stimulus remain relevant because agentic AI still needs structured verification environments within which to operate.
Human oversight must be designed into the workflow
One of the strongest conclusions of the September column is that human review should not appear only at the end of an autonomous process.
It should be built into the verification flow.
A controlled agentic environment needs clear authority boundaries, traceable inputs and explicit approval points. Engineers should be able to establish which actions an agent can perform independently and which decisions require review.
That distinction becomes particularly important when actions could alter the verification argument itself.
Changing a formal assumption, accepting a waiver, modifying verification intent or closing an engineering issue can directly affect sign-off confidence. These should not become invisible automated decisions simply because an AI system is capable of recommending them.
The workflow must also distinguish between different levels of certainty. A direct simulator or formal-engine result is different from an AI-generated explanation of that result, and both are different again from a speculative recommendation for the next action.
Reproducibility matters for the same reason.
If engineers cannot reconstruct how an AI-assisted conclusion was produced from controlled inputs, that conclusion should not become part of the sign-off evidence.
Agentic DV EDA products are beginning to emerge
The move towards agentic engineering is now visible across the EDA market.
Mike’s column discusses developments from Cadence, Synopsys, Siemens and MooresLab AI as examples of the industry moving from isolated AI functions towards systems capable of coordinating multiple engineering activities.
The strategic change is more important than any individual product.
AI is beginning to move from task-level assistance towards workflow-level orchestration.
That direction is also visible in recent industry discussion. Siemens, for example, has been discussing agentic AI specifically in the context of the future of design and verification.
For verification organisations, this means evaluation criteria will need to expand. Teams will need to consider not only model quality or generated-code quality, but also tool authority, context management, provenance, reproducibility, approval gates and integration with existing verification methodology.
Where AlpinumDV fits into this direction
Alpinum is also developing practical AI-assisted verification workflows through AlpinumDV.
AlpinumDV can currently generate verification plans, UVM testbench components, assertions, coverage models and supporting verification collateral. It also supports testbench validation, mutation testing, dynamic stimulus generation and coverage closure.
Recent AlpinumDV evaluation work has focused not simply on generation, but on whether generated verification environments can expose controlled RTL changes through mutation testing. That provides a different form of evidence from simply measuring how quickly AI can produce testbench code.
The next AlpinumDV release is intended to extend these capabilities towards full SoC design verification, encompassing bus fabric, bridge, peripherals and software-driven verification.
Alpinum’s Online Submission Portal provides the controlled execution environment around these workflows, enabling approved verification jobs to be submitted and the resulting logs and evidence to be reviewed. The wider Alpinum Tools area brings the Online Submission Portal and AlpinumDV workflows together within a structured engineering environment.
The objective is not autonomy for its own sake.
It is to explore how AI can shorten verification loops whilst preserving traceability, engineering review and accountable sign-off.
What should verification teams take from this?
Agentic AI has the potential to change the operating model of design verification.
Instead of engineers manually coordinating every transition between planning, generation, execution, debug and coverage analysis, controlled agents may increasingly help keep those workflows moving.
But greater execution autonomy also increases the importance of defining authority.
Verification teams will need to be clear about what an agent may read, what it may generate, which tools it may invoke, which artefacts it may modify and which decisions it must return to an engineer.
The most important boundary remains the same one established in Mike’s previous Electronics World column:
AI may accelerate the route from specification to evidence, but engineering responsibility cannot be delegated with the workflow.
The future of agentic verification is therefore unlikely to be an AI system independently declaring a semiconductor design correct.
A more credible direction is a controlled engineering environment where agents help plan, execute and analyse verification activity, while engineers continue to own verification intent, methodology, risk acceptance and final sign-off.
Continue the Electronics World discussion
Mike Bartley’s September 2026 Electronics World column develops Alpinum’s continuing discussion of how AI is changing semiconductor design verification—from measurable AI adoption, through engineering intent and sign-off, and now towards controlled verification agents and workflow orchestration.
Read the full September 2026 Electronics World column:
Agentic AI is changing design verification – Electronics World September 2026
For the previous article in the series, read:
AI-Assisted Verification: Why Sign-Off Still Depends on Engineering Intent
For practical AI-assisted verification workflows, explore:
Alpinum Tools and AlpinumDV
Teams assessing how AI can be introduced into existing verification environments can also explore Alpinum’s AI in Design Verification services and discuss controlled adoption, verification methodology, tool integration and engineering governance with Alpinum.

Written by : Mike Bartley
Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification.
Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients.
Mike started Alpinum in April 2016 to deliver a range of start-of-the art industry solutions:
Alpinum AI provides tools and automations using Artificial Intelligence to help companies reduce development costs (by up to 90%!) Alpinum Services provides RTL to GDS VLSI services from nearshore and offshore centres in Vietnam, India, Egypt, Eastern Europe, Mexico and Costa Rica. Alpinum Consulting also provides strategic board level consultancy services, helping companies to grow. Alpinum training department provides self-paced, fully online training in System Verilog, UVM Introduction and Advanced, Formal Verification, DV methodologies for SV, UVM, VHDL and OSVVM and CPU/RISC-V. Alpinum Events organises a number of free-to-attend industry events
You can contact Mike (mike@alpinumconsulting.com or +44 7796 307958) or book a meeting with Mike using Calendly (https://calendly.com/mike-alpinum-consulting).
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