The Design Verification (DV) course (delivered by Dr. Mike Bartley) met our main objective which was to upskill our graduate and junior verification engineers to have the knowledge and understanding of verification to start supporting projects in the shortest time possible whilst minimising initial training and supervision time from our senior engineers.

The Design Verification course (delivered by TechWorks Academy) met our main objective which was to upskill our graduate engineers to have the knowledge and understanding of the application of VHDL and OSVVM in verification environments, the course also covered SV and UVM. Course understanding was helped with the extensive set of examples and exercises which allowed the participants to progress from initially simple, to complex design and test benches – which included debug and fix.

It was s great opportunity to learn from someone who has a vast knowledge and industrial experience in CPU’s, SOC’s, and software (down to assembler), and their verification. Part1 of the course is an introduction to CPU concepts and an overview of state-of-the-art CPU verification practices. Personally, my introduction to mutation testing and constrained pseudo-random stimulus generation techniques for CPU’s by taking this course were completely new things and justified the cost of the course by themselves, even though they represent less than 10% of the content!. Each lecture in the course has both quizzes and forms which helped to ensure that I understood both the concepts and their application in real-world context.