RISC-V Verification, Zurich
As the semiconductor industry increasingly embraces chiplet-based architectures, the complexity of system integration and verification has grown exponentially. Verifying these modular systems demands new approaches, tools, and collaboration across design and verification teams.
This online edition of DVClub will focus on the challenges, strategies, and breakthroughs in verifying chiplet-based systems. Industry leaders and verification experts will share real-world case studies, emerging methodologies, and practical insights into ensuring functionality, performance, and interoperability in this rapidly evolving domain.
Whether you’re working on multi-die integration, interconnect protocols, or verification frameworks for heterogeneous chiplet systems, this event offers a valuable opportunity to learn, connect, and stay ahead of the curve.
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Agenda (GMT)
Time | Session Description | Presentations | Videos |
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12.00 | Start, Arrival, registration, networking, light refreshments | ||
13:00 | Derisking the RISC-V by Puneet Goel, Coverify |
View PDF | View Video |
13:30 | Advanced RISC-V Verification by Dave Kelf, Breker Systems |
View PDF | View Video |
14:00 | Extending a RISC-V Industrial-Grade Core (without breaking it) by Mike Thompson and Cairo Caplan, Open HW Group |
View PDF | View Video |
14:30 | Security verification of AXI on RISC-V by Melisande Zonta-Roudes, ETH Zurich |
View PDF | View Video |
15:00 | Break with refreshments/networking | ||
15:30 | Automatic ISA analysis for Secure Context Switching by Neelu Shivprakash Kalani, EPFL & IBM Research |
View PDF | View Video |
16:00 | Proof Strategies in the Comprehensive Formal Verification of the Ibex Processors by Louis-Emile Ploix, lowRISC / University of Oxford |
View PDF | View Video |
16:30 | Strengthening RISC-V with Formal Verification for your next tape out:Properties, Coverage, and Model Checking by Cristina Augello & Stefano Moncalvo, STMicroelectronics |
View PDF | View Video |
17:00 | MileSan: Detecting Exploitable Microarchitectural Leakage via Differential Hardware-Software Taint Tracking by Tobias Kovats, ETH Zurich |
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17:15 | Pathfinder: Constructing Cycle-accurate Taint Graphs for Analyzing Information Flow Traces by Katharina Ceesay-Seitz, ETH Zurich |
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17:30 | Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection by Matej Bölcskei, ETH Zurich |
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17:40 | Refreshments/networking |