Format
Live Online Training
Duration
1 Session
Total Training Time
4 Hours
Session Length
1 × 4-Hour Session

Apply software testing and verification techniques to embedded and real-time systems where timing, resource constraints, hardware interaction and fault behaviour become part of the verification problem.

This four-hour module combines embedded static analysis with dynamic and real-time testing, covering MISRA-C, constrained-target analysis, stack usage, QEMU-based emulation, FreeRTOS behaviour, WCET, interrupt latency and hardware-interface testing.

Participants first analyse a sample embedded driver for coding, resource and reentrancy issues, then exercise the same software dynamically through an emulated hardware environment.

The module concludes with a static and dynamic verification package for a sample embedded UART/CAN driver, combining MISRA-C compliance evidence with timing and fault-injection results.

View the Full Software Testing & Verification Programme

What You Will Learn

Module 7 adapts the testing techniques developed earlier in the programme to embedded and resource-constrained systems.

Participants examine both the software implementation and its real-time behaviour, learning how embedded verification must account for coding rules, resource use, hardware interaction, scheduling and timing.

Topics

  • MISRA-C rule emphasis for embedded and resource-constrained targets
  • Static analysis for interrupt service routines, register-level code and DMA
  • Stack usage estimation and cross-compilation toolchain configuration
  • Embedded Rust (no_std) static analysis
  • Hardware-in-the-Loop (HIL) testing concept; QEMU-based emulation
  • Dynamic GPIO/UART/SPI/I2C/CAN testing
  • FreeRTOS task, priority and queue/semaphore testing
  • Worst-Case Execution Time (WCET) and real-time deadline validation
  • Interrupt latency testing; stress testing and fault injection

Lab 1: Embedded Static Analysis (MISRA-C)

Learning Objectives: MISRA-C, static analysis for constrained targets, stack usage estimation

Description: Run a MISRA-C check against a sample embedded driver and resolve the flagged violations.

Tasks

  • Run cppcheck/clang-tidy against a sample UART driver with a cross-compilation configuration.
  • Identify one MISRA-C Rule 8 (declarations) violation and resolve it.
  • Identify one unsafe pointer arithmetic finding and resolve it.
  • Estimate worst-case stack usage for one function statically.
  • Review one interrupt service routine for reentrancy hazards.
  • Record MISRA compliance status for the driver in a compliance matrix.

Extension Tasks

  • Apply the same MISRA-C check to an equivalent embedded Rust no_std module using clippy.
  • Draft a MISRA deviation record for one accepted exception.

Topics Covered

MISRA-C, Static Analysis for ISRs, Stack Usage Estimation

Open Source Recommendation

cppcheck and clang-tidy configured for cross-compiled ARM targets, plus clippy for the embedded Rust comparison.

Lab 2: HIL/QEMU Dynamic Testing & Real-Time Validation

Learning Objectives: QEMU, HIL-style testing, FreeRTOS, WCET, interrupt latency

Description: Run the Lab 1 driver under QEMU emulation and validate its real-time behaviour.

Tasks

  • Run the sample firmware under QEMU and validate a basic GPIO toggle sequence.
  • Perform a loopback test on the UART driver.
  • Send and validate a sample CAN frame, including one malformed-frame case.
  • Reproduce a priority inversion scenario on a FreeRTOS task set.
  • Measure task execution timing and compare it against a WCET estimate.
  • Measure interrupt latency from trigger to handler execution.

Extension Tasks

  • Inject a simulated hardware fault and observe fail-safe behaviour.
  • Run a sustained high-frequency interrupt stress scenario.

Topics Covered

QEMU, FreeRTOS Testing, WCET, Interrupt Latency

Open Source Recommendation

QEMU for ARM emulation and FreeRTOS itself, both open-source.

Module 7 Coverage Matrix

TopicLab 1Lab 2
Embedded Static Analysis (MISRA-C) 
Stack & Resource Analysis 
HIL/QEMU Dynamic Testing 
FreeRTOS Real-Time Testing 
Fault Injection 

 

Module Project: Embedded Static & Dynamic Verification Package

Static and dynamic verification package for a sample embedded UART/CAN driver — MISRA-C compliance evidence plus a QEMU-based dynamic test report covering timing and fault-injection results.

The project connects source-level analysis with execution-level evidence.

Participants progress through:

Embedded source code

MISRA-C & static analysis

Resource and ISR review

QEMU-based execution

FreeRTOS & interface testing

Timing measurements

Fault injection

Verification evidence

This creates a practical example of how embedded verification requires both static and dynamic evidence.

From General Integration Testing to Embedded Verification

Module 6 examines software integration across protocols, networks, middleware and data systems.

Module 7 moves into a different execution environment: embedded and real-time software interacting closely with hardware and timing constraints.

The programme progression becomes:

Integration & Protocol-Level Testing

Embedded Static Analysis

Hardware/Interface Behaviour

Real-Time Scheduling & Timing

Fault Behaviour

This makes Module 7 clearly distinct from general integration or application testing.

Embedded Static Analysis and MISRA-C

Static analysis in embedded systems often has to account for more than general code quality.

The Module 7 curriculum applies analysis to areas including:

  • Interrupt service routines
  • Register-level code
  • DMA-related software
  • Stack usage
  • Pointer behaviour
  • Cross-compiled targets
  • MISRA-C compliance evidence

Participants also review reentrancy hazards and record compliance status in a structured matrix.

This builds upon the general static-analysis skills introduced in Module 2: Static Analysis & Code Quality, but applies them specifically to constrained embedded targets.

HIL Concepts and QEMU-Based Testing

The module introduces the concept of Hardware-in-the-Loop (HIL) testing while using QEMU-based emulation for practical exercises.

Participants use the emulated environment to validate behaviour including:

  • GPIO activity
  • UART communication
  • CAN traffic
  • malformed CAN frames
  • FreeRTOS scheduling behaviour
  • timing

This enables dynamic testing of embedded software behaviour without requiring the entire exercise to depend on proprietary hardware or commercial toolchains.

FreeRTOS and Real-Time Behaviour

Correct functional output is only part of the verification problem in real-time software.

Module 7 therefore includes FreeRTOS-related testing around:

  • Tasks
  • Priorities
  • Queues/semaphores
  • Priority inversion
  • Execution timing
  • Interrupt behaviour

The practical lab specifically asks participants to reproduce a priority-inversion scenario and examine real-time timing evidence.

WCET and Interrupt-Latency Validation

Real-time verification must consider not only what software does, but also when it does it.

The module therefore includes:

Worst-Case Execution Time (WCET)
for reasoning about task execution against real-time expectations.

Interrupt latency
for measuring the delay between an interrupt trigger and handler execution.

Participants compare measured task timing against a WCET estimate and measure interrupt latency directly within the practical exercise.

Keep this content focused on verification rather than expanding into a general real-time systems theory page.

Fault Injection and Stress Testing

The module also introduces controlled failure conditions.

Extension activities include:

  • Simulated hardware fault injection
  • Fail-safe behaviour
  • Sustained high-frequency interrupt stress

This moves verification beyond normal operating behaviour and gives participants experience observing software under abnormal embedded-system conditions.

How Module 7 Connects With Other Modules

Module 2: Static Analysis & Code Quality

Module 2 introduces cppcheck, clang-tidy and clippy across general software environments.

Module 7 reuses those concepts for cross-compiled, resource-constrained embedded targets.

Module 6: Integration & Protocol-Level Testing

Module 6 introduces broader protocol and CAN/MQTT/REST integration contexts. Module 7 narrows attention to embedded hardware interfaces and real-time execution.

Module 8: IoT & Networking Applications Testing

Embedded devices often become part of larger connected systems. Module 8 expands the scope into device/gateway/cloud testing, OTA updates, connectivity resilience, load and failover testing.

Module 10: Automotive/ADAS Safety-Critical Testing

Module 10 later applies embedded and safety-related concepts specifically within automotive and ADAS environments.

Frequently Asked Questions

What does the Embedded & Real-Time Systems Testing module cover?

The module covers embedded static analysis, MISRA-C, stack/resource analysis, QEMU-based dynamic testing, FreeRTOS, hardware-interface testing, WCET, interrupt latency and fault injection.

Does the module include MISRA-C?

Yes. Participants analyse a sample embedded driver, identify and resolve MISRA-C-related findings and record compliance status in a compliance matrix.

Is embedded Rust included?

Yes. The curriculum introduces embedded Rust no_std static analysis, and an extension exercise applies analysis to an equivalent embedded Rust module using clippy.

What is QEMU used for?

QEMU is used to run sample firmware in an emulated environment and perform dynamic verification exercises including GPIO, UART, CAN and real-time behaviour.

Does the module cover Hardware-in-the-Loop testing?

The module introduces the HIL testing concept and performs HIL-style dynamic testing using QEMU-based emulation.

Is FreeRTOS testing included?

Yes. The curriculum covers FreeRTOS task, priority and queue/semaphore testing and includes a practical priority-inversion scenario.

What is WCET testing?

The module includes Worst-Case Execution Time and real-time deadline validation. Participants compare measured task execution timing against a WCET estimate.

Does the module measure interrupt latency?

Yes. Participants measure interrupt latency from the trigger to handler execution.

Is CAN testing included?

Yes. The dynamic laboratory includes sending and validating a CAN frame, including a malformed-frame test case.

Does the module cover fault injection?

Yes. Extension work includes simulated hardware fault injection and observation of fail-safe behaviour.

What is the Module 7 project?

The project is a static and dynamic verification package for a sample embedded UART/CAN driver, combining MISRA-C compliance evidence with QEMU-based timing and fault-injection results.

Continue Your Software Testing & Verification Path

Apply verification techniques to embedded and real-time systems, then extend those capabilities into connected device, gateway and cloud applications.