Security Verification | DV Club Zurich 2026

Security verification is becoming a critical priority as semiconductor systems, RISC-V processors, SoCs, cryptography extensions, and connected devices grow more complex. Verification teams must now consider not only functional correctness, but also hardware security, vulnerability detection, confidentiality assurance, and trust in system-level behaviour.

DV Club Zurich 2026 brought together researchers, semiconductor engineers, EDA specialists, and verification professionals to discuss practical approaches for verifying security properties in modern chip design. The programme covered RISC-V cryptography extensions, deterministic fuzzing, custom instruction set extensions, hardware security assurance, SoC security, vulnerability detection, OSVVM co-simulation, CHERI-CVA6 formal verification, and transparent software emulation.

For organisations working on security-critical designs, Alpinum also provides security services, formal verification services, and wider design verification support.

This post-event page provides access to the DV Club Zurich agenda, presentation slides, and related security verification resources from Alpinum Consulting. Engineers interested in related RISC-V capability may also explore Alpinum’s RISC-V Verification training and RISC-V overview resources.