RISC-V Verification

RISC-V is rapidly transforming semiconductor design with its open and extensible instruction set architecture. As adoption grows across commercial, automotive, academic, and open-source projects, verification teams need robust methodologies to ensure processor quality, reliability, security, and system-level correctness. For teams building capability in this area, Alpinum also provides RISC-V Verification training

DV Club Cambridge 2026 brought together leading RISC-V verification experts, EDA specialists, semiconductor engineers, and researchers to discuss practical techniques for verifying RISC-V cores and complex SoC subsystems. The programme covered RISCV-DV, system verification, formal verification, hardware Trojan detection, OSVVM co-simulation, Jasper-based verification, Ibex tape-out experience, Sail-RISC-V modelling, and CHERI RISC-V processor verification.

This resource page provides access to the DV Club Cambridge agenda, presentation slides, video recordings, and related RISC-V verification resources from Alpinum Consulting. Engineers interested in broader verification skills may also explore Alpinum’s Design Verification training and RISC-V overview resources.

For more useful event resources, please visit DV Club Cambridge 2026.

Event at a Glance:

  • Fri 5 Jun 2026

  • 12:00 PM – 6:00 PM BST

  • University of Cambridge 15 J.J. Thomson Avenue, Cambridge, CB3 0FD

Agenda (GMT)

TimeSession DescriptionPresentationsVideos
12:00Arrival, registration, networking, light refreshments  
13:00Max RISCV-DV by Puneet Goel, Coverify Systems Technology LLPView PDFView recording
13:20Applying System Verification Techniques to RISC-V Core and Subsystem Validation by David Kelf, Breker Verification Systems

View PDF
White paper

View recording
13:50Reliable Hardware Trojan Detection for RISC-V Processors using Formal Verification by Christian Appold, DENSO AUTOMOTIVE Deutschland GmbHView PDFView recording
14:10RISC-V software and logic co-development with OSVVM co-simulation by Simon Southwell, Wyvern SemiconductorsView PDFView recording
14:30Foundational verification of logical equivalence checking by Michalis Pardalos, Imperial College LondonView PDFView recording
14:50RISC-V Verification with Jasper by Nupur Verma, CadenceView PDFView recording
15:15Break with refreshments/networking  
15:45Ibex: going from university core to commercial tape-out by Dr Marno van der Maas, lowRISCView PDFView recording
16:10From the Sail-RISC-V spec to a Verilog model for verification by Dr Alasdair Armstrong, University of CambridgeView PDFView recording
16:40Formal Verification of CHERI RISC-V Processors by Prof Tom Melham, University of OxfordView PDFView recording
17:10Refreshments/networking