Hardware Assisted Verification Test Solutions
As SoCs grow in complexity, with multiple processors, accelerators, and processing subsystems, the need for efficient verification strategies has never been greater. Hardware Assisted Verification (HAV) — leveraging hardware emulators or FPGA prototypes — enables faster and more comprehensive RTL verification and hardware-software co-verification by running test generation directly on the hardware.
This session will explore real-world customer use cases from Synopsys, showcasing cutting-edge technologies and integrations that support both Arm- and RISC-V–based SoCs. With HAV products seeing rapid adoption in verification flows, this theme offers valuable insights for teams looking to improve performance, scalability, and coverage in their verification processes.
Time Details
| Time | Session Description | Presentations | Videos |
|---|---|---|---|
| 12:00 | Introduction | ||
| 12:00 | RISC-V Hardware Assisted Verification: Integration with Test Generation for Faster Sign-Off by Aimee Sutton, Synopsys | View PDF | Watch |
| 12:20 | Emulation: from C Tests to Tapeout – a Case Study by Antoine Madec, Axelera AI | View PDF | Watch |
| 12:40 | Scaling Verification for High-Performance Chips: Why Hardware-Assisted, Real-Time Visibility Isn’t Optional. by Frederic Leens, Exostiv Labs | View PDF | Watch |
| 13:00 | Accelerating FPGA-prototype bring-up time with implementation software by Romain Petit, Siemens | View PDF | Watch |
| 15:00 | END |
