High Performance Computing and Automotive
As the demands on High-Performance Computing (HPC) and automotive systems grow, so does the design and verification complexity needed to meet them. From advanced driver-assistance systems (ADAS) and autonomous driving platforms to data-intensive applications powered by HPC, engineers face the challenge of ensuring speed, reliability, security, and safety in increasingly sophisticated environments.
Join us at DVClub Vietnam for a deep dive into cutting-edge verification strategies shaping the future of HPC and automotive design. This session will explore methodologies for verifying high-throughput architectures, optimising performance for AI and machine learning workloads, and ensuring compliance with safety and security standards critical to the automotive sector. We’ll also discuss the role of AI-driven verification, hybrid simulation, formal verification, and emulation techniques in accelerating cycles, improving coverage, and delivering robust designs faster.
Whether you are working on complex automotive SoCs, HPC platforms, or cross-industry innovations, this session will provide actionable insights and proven approaches to help you manage complexity, enhance reliability, and meet the ever-increasing demands of performance-driven markets.
Agenda
| Time | Session Description | Presentations | Videos |
|---|---|---|---|
| 12.00 | Arrival, registration, networking | ||
| 13.00 | Semiconductor Education in VNUHCM-UIT: A case study with Design Verification Course by Minh Son NGUYEN, Vietnam National University at HCMCity – University of Information | View PDF | Video |
| 13:30 | Agentic AI for Next-Generation Chip Verification: Verisium Powered by JedAI by Anika Sunda, Cadence Vietnam | View PDF | Video |
| 14:00 | Enhancing Verification Efficiency with AutoFocus on the Verisium Platform by Nguyen Hoang Nghia, Renesas Design Vietnam | View PDF | Video |
| 14:30 | Marvell’s Accelerated Infrastructure for AI Data Center by Quang-Dam Le, Marvell Technology Vietnam | Not available | Video |
| 15:00 | Break with refreshments/networking | ||
| 15:30 | Unified Test Vector Framework Across Multiple Testbench Levels and Software Validation by Hung Le, BOS Semiconductors Vietnam | View PDF | |
| 16:00 | Practical experience sharing of adopting Jasper on register/connection verification by Richard An, Realtek Semiconductor Corp. | View PDF | Video |
| 16:30 | Using AI in Verification by Mike Bartley, Alpinum | View PDF | Video |
| 17:00 | Refreshments & Pizza/networking |
