What is VHDL?

VHDL (VHSIC Hardware Description Language) is a powerful hardware description language used for designing and simulating digital systems, such as FPGAs (Field- Programmable Gate Arrays) and ASICs (Application-Specific Integrated Circuits), according to Aldec, (2025). It enables engineers to describe the behavior, structure, and functionality of digital circuits at various levels of abstraction, from high-level algorithms to low-level gate implementations. Widely adopted in the semiconductor industry, VHDL is known for its robust syntax and support for complex modeling, making it an essential tool for designing reliable and efficient hardware systems.

Benefits of VHDL

VHDL offers numerous benefits that make it an indispensable tool for hardware design and verification, as highlighted by Aldec, (2025). Its versatility allows engineers to model digital systems at multiple levels of abstraction, from system-level descriptions to detailed gate-level implementations. VHDL promotes design reusability through modular structures, enabling efficient development and scalability of complex systems. With its strong typing and rigorous syntax, VHDL helps identify errors early in the design process, enhancing reliability. Additionally, its compatibility with simulation tools ensures thorough testing before hardware implementation, making it a valuable asset for FPGA and ASIC development in critical applications.

Why Choose VHDL?

VHDL offers several advantages that make it an ideal choice for hardware design and verification, as mentioned by ALSE and Cuzeau, (2005). Its standardized syntax and rigorous structure ensure reliability and precision in digital system modeling. Whether you’re working on simple unit tests or complex system-level designs, VHDL’s scalability makes it adaptable to various applications. VHDL’s strong typing and compatibility with industry-standard simulation tools provide a robust framework for error detection and testing, improving the efficiency and accuracy of your verification process. Additionally, VHDL’s long-standing use in the industry ensures a wealth of resources and community support, making it a trusted language for FPGA and ASIC development.

Introduction to VH/26990 Verification Methodology

The VH/26990 verification methodology, presented by LP Lewis of SynthWorks, is a widely adopted approach for enhancing VHDL verification processes, according to Lewis, (2024). With over 30 years of expertise in VHDL design and verification, Lewis emphasized the importance of this methodology in streamlining and improving testing efficiency. VH/26990 offers a structured framework that simplifies testbench creation, integrates reusable components, and automates testing, reducing errors and accelerating project timelines.

Addressing Common Verification Challenges

Verification accounts for 40-50% of project time, with a significant portion of FPGA projects encountering critical bugs, as mentioned by Lewis, (2024). VH/26990 addresses these challenges through transactions, abstracting, and simplifying test case development. This approach reduces the brute force nature of traditional testing and makes testbenches more readable and less error-prone. VH/26990 ensures rigorous testing for safety-critical projects by focusing on functional coverage and self- checking mechanisms.

Comprehensive Verification Framework

The VH/26990 framework mirrors System Verilog in structure, with reusable verification components implementing interface signaling, as highlighted by Lewis, (2024). Each test case is built as a separate architecture, enabling concurrency and robust capability. The methodology’s Model Independent Transaction Library (MIT) standardizes transaction interfaces across various protocols, streamlining test creation and enhancing component reuse across different testing levels, from RTL to system-level verification.

Test Automation and Reporting

Test automation in VH/26990 leverages TCL-based scripting, enabling seamless integration with multiple simulators like GHDL, Aldec, and Synopsys VCS, as emphasized by Lewis, (2024). This capability simplifies regression testing and ensures consistent results across platforms. Detailed test reports, generated in HTML and XML formats, provide clear pass/fail indicators and integrate with continuous integration tools. The End of Test Reports feature consolidates test results, offering a comprehensive summary of affirmations, alerts, and coverage metrics.

Benefits and Adoption of VH/26990

VH/26990 stands out for its readability, reuse, and flexibility, making it accessible to any VHDL engineer, as noted by Lewis, (2024). Its transaction-based methodology

supports directed and constrained random testing, providing powerful capabilities that rival other verification languages. With extensive resources on GitHub and tailored training offered by SynthWorks, engineers can incrementally adopt VH/26990 to enhance their verification processes while ensuring robust and reliable designs.

Note: For those interested in the latest advancements in verification technologies, the FPGA Verification Event 2025 (Verification Futures UK) offers an excellent opportunity to gain insights into cutting-edge verification practices.

References

Aldec. (2025). Open Source VHDL Verification Methodology (OSVVM) – Functional Verification – Solutions – ALDEC.

https://www.aldec.com/en/solutions/functional_verification/osvvm

ALSE, & Cuzeau, B. (2005). VHDL Design Rules & Coding Style. http://www.alse- fr.com

Lewis. (2024). SynthWorks – Why should our team be using VHDL+OSVVM for verification. In https://alpinumconsulting.com/fpga-front-runner-sep24/.

Author

  • Mike Bartley

    Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification. Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP. Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions:

    Alpinum AI provides tools and automations using Artificial Intelligence to help companies reduce development costs (by up to 90%!)

    Alpinum Services provides RTL to GDS VLSI services from nearshore and offshore centres in Vietnam, India, Egypt, Eastern Europe, Mexico and Costa Rica.

    Alpinum Consulting also provides strategic board level consultancy services, helping companies to grow.

    Alpinum training department provides self-paced, fully online training in System Verilog, UVM Introduction and Advanced, Formal Verification, DV methodologies for SV, UVM, VHDL and OSVVM and CPU/RISC-V.

    Alpinum Events organises a number of free-to-attend industry events

    You can contact Mike (mike@alpinumconsulting.com or +44 7796 307958) or book a meeting with Mike using Calendly (https://calendly.com/mike-alpinumconsulting).

  • Mukul Kumar

    Design Verification (DV) Engineer at Tessolve Semiconductor with 3 years of semiconductor industry experience, specializing in UVM test benches, RTL design verification. Currently working in the Tessolve Centre of Excellence (CoE) on open-source RISCV projects (such as IBEX and PICOSOC) and on using AI to generate Portable Stimulus Standard (PSS) test benches from design specifications.