AMS verification system-level analysis mixed-signal chip design DESN London event
Published On: 3rd April 2026|Last Updated: 3rd April 2026|By |
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The DESN “Designing the Future: Analogue Mixed Signal (AMS)” event in London brought together engineers, architects, and industry leaders to explore the evolving challenges of analogue and mixed-signal design. While discussions covered architecture, applications, and emerging technologies, one theme stood out clearly: verification of AMS systems is becoming increasingly complex and requires a more structured, system-level approach.

This blog highlights the key technical insights from the event and their implications for engineering teams working on modern semiconductor designs.

Why AMS Verification Is Becoming More Challenging

Analogue and mixed-signal systems sit at the intersection of continuous and discrete behaviour. Unlike purely digital systems, verification must account for:

  • Interaction between analogue and digital domains
  • Sensitivity to noise, variation, and environmental conditions
  • Behaviour across multiple abstraction levels

As system complexity increases, traditional verification approaches become harder to scale. Teams often rely on fragmented methods, which can introduce coverage gaps and reduce confidence at sign-off.

This reinforces the need for structured verification methodologies such as those applied in Alpinum Consulting’s work in https://alpinumconsulting.com/services/designverification/

System-Level Challenges Are Now Central

A key takeaway from the event was that many failures no longer originate within individual blocks, but at the interfaces between systems.

Challenges discussed included:

  • Signal integrity and interference across domains
  • Integration of analogue, digital, and software components
  • Increasing use of multi-die and heterogeneous architectures

These issues require a shift from circuit-level thinking to system-level verification strategies, where behaviour is analysed across the full design context rather than in isolation.

The Role of AI and Automation in AMS Workflows

Another strong theme was the growing role of AI and automation in supporting design and verification.

Modern toolchains are evolving to enable:

  • Earlier verification in the design cycle
  • Improved co-simulation between analogue and digital domains
  • Faster identification of critical design sensitivities

AI-driven approaches are not replacing engineers, but augmenting decision-making by enabling more efficient exploration of design trade-offs and constraints.

Structured Design Migration and Verification Approaches

A notable presentation highlighted structured methodologies for design migration between technologies.

Key elements included:

  • Accurate device mapping between source and target nodes
  • Simulation-driven validation to guide decisions
  • Sensitivity-based optimisation to focus on critical elements
  • Preservation of layout intent to maintain performance

These approaches demonstrate how structured engineering processes can significantly reduce iteration cycles while maintaining design integrity.

Industry Direction: Growth, Complexity, and Talent Gaps

The event also reflected broader semiconductor trends:

  • Growth driven by AI, electrification, and advanced computing
  • Increasing demand for complex mixed-signal systems
  • Shortage of experienced analogue engineers

As systems scale, the combination of technical complexity and limited expertise makes verification discipline even more critical.

What This Means for Engineering Teams

For engineering teams, the implications are clear:

  • Verification must be planned at the system level, not added late
  • Integration risks must be addressed early in the lifecycle
  • Structured methodologies are essential for scalability
  • Collaboration across analogue, digital, and system teams is critical

Teams that continue to rely on ad-hoc or fragmented approaches will struggle to maintain confidence at sign-off as complexity grows.

For those looking to strengthen capability in this area, targeted training and structured methodologies can help bridge the gap between theory and practical application:
👉 https://alpinumconsulting.com/services/training/

Conclusion

The DESN AMS event highlighted a clear shift in the industry. Verification is no longer a supporting activity. It is a central engineering discipline that determines whether complex systems can be delivered with confidence.

As analogue and mixed-signal designs continue to evolve, success will depend on:

  • Structured verification strategies
  • System-level thinking
  • Effective use of automation and AI
  • Continuous development of engineering capability

For organisations working at the forefront of semiconductor design, adapting to this shift is not optional. It is essential.

Explore More

For further insights on verification challenges and methodologies:
👉 https://alpinumconsulting.com/resources/blogs/verification/

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Written by : Mike Bartley

Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification.

Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients.

Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions:

Alpinum AI provides tools and automations using Artificial Intelligence to help companies reduce development costs (by up to 90%!) Alpinum Services provides RTL to GDS VLSI services from nearshore and offshore centres in Vietnam, India, Egypt, Eastern Europe, Mexico and Costa Rica. Alpinum Consulting also provides strategic board level consultancy services, helping companies to grow. Alpinum training department provides self-paced, fully online training in System Verilog, UVM Introduction and Advanced, Formal Verification, DV methodologies for SV, UVM, VHDL and OSVVM and CPU/RISC-V. Alpinum Events organises a number of free-to-attend industry events

You can contact Mike (mike@alpinumconsulting.com or +44 7796 307958) or book a meeting with Mike using Calendly (https://calendly.com/mike-alpinumconsulting).

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