Staffing Solutions – Europe
| Domain | Code | Years | Country | Main skills |
| DV | EU1 | 6+ | Greece | Expertise: Digital/ASIC/FPGA Design & Verification Languages/Tools: SystemVerilog, Verilog, VHDL, UVM, SVA, Perl, Python, Bash, Tcl Tools: Synopsys, Cadence, Mentor, Questa, VCS, PrimeTime, DVE, Verdi, ClearCase Experience: Extensive SoC/ASIC/FPGA verification, coverage-driven and constraint-random verification, assertion-based verification |
| DV | EU2 | 23+ | Greece | Expertise: SoC & FPGA Design, Analog/Mixed-Signal Verification Tools: Cadence (Virtuoso, ADE), Keysight (ADS), MATLAB, Simulink Skills: RF and mixed-signal circuit design, layout, lab measurements, component selection, ESD/EMC compliance Specialties: LNA, PA, RF switches, Oscillators, VCOs, ADCs, DACs, ESD |
| DV | EU5 | 25y | Austria | Expertise: RTL Design & Simulation, Functional Verification Tools: VCS, Verdi, Questa, PrimeTime, Power Compiler Languages: SystemVerilog, VHDL, Specman/e Protocols: DDR, AXI, AHB, SPI, I2C, USB Experience: Assertion-based verification, FSM and datapath verification, regression infrastructure setup |
| DV | EU6 | 25y | Serbia | Expertise: SoC/ASIC Verification, Embedded Systems, Protocol Verification Languages/Tools: SystemVerilog, UVM, eRM, VHDL, Perl, C/C++, Verdi Tools: Synopsys, Cadence, Mentor, Specman Protocols: USB, SPI, I2C, CAN, UART, AMBA Highlights: Digital/AMS co-verification, IP and SoC-level validation, formal verification |
| DV | EU7 | 8+ | Serbia | Expertise: SoC Verification, Automotive Chip Development Languages/Tools: Specman, SystemVerilog, UVM, Java Experience: RTL simulation, layout tools, production flow Strengths: Lead verification strategy, stakeholder collaboration, technical reviews |
| DV | EU8 | 7+ | Poland | Expertise: Protocol & Interface Verification, DSP-based Applications Languages/Tools: Verilog, VHDL, UVM, Python, C++ Experience: Ethernet, PCIe, USB, DDRx, Serial protocols Highlights: SoC integration, embedded systems, test automation |
| DV | EU9 | 10+ | Finland | Expertise: System-Level Verification, IP/Sub-System Validation Languages/Tools: SystemVerilog, UVM, VHDL, Specman/e Experience: Functional coverage, block-level to full-chip verification Strengths: Team leadership, collaboration, mentoring, debug & simulation |
| DV | EU10 | 17+ | Romania | Expertise: Mixed-Signal SoC Verification, AMS Modeling Languages/Tools: Verilog, SystemVerilog, C++, Bash, Java, Python Tools: Virtuoso, Spectre, Matlab, PSpice Experience: Integration of analog/digital subsystems, modeling of analog behavior |
| DV | EU11 | 29+ | UK | Expertise: Digital IC Verification, Functional Safety, System-Level Validation Languages/Tools: SystemVerilog, UVM, Tcl, Shell Tools: Questa, SimVision, DVT, JavaScript Protocols: AMBA, DDR, USB, SPI Experience: End-to-end project execution, verification planning, testbench creation |
| DV | EU12 | 6+ | TBC | Expertise: RTL Design and Verification, SoC Integration Languages/Tools: Verilog, VHDL, UVM, Specman/e Experience: FPGA/ASIC development cycles, debug and simulation, hardware bring-up Protocols: UART, SPI, I2C, AHB, AXI Strengths: Clear understanding of functional flows, RTL development, simulation, and assertion verification |
| ESE | EUESE1 | 16+ | România | Skills: Embedded systems development, device drivers, firmware architecture, low-level debugging, real-time systems, software integration, bootloaders, communication protocols, build systems, diagnostics, software quality assurance, hardware interfacing
Languages: C, C++, Python, Assembly, C#, Shell scripting Experience: AUTOSAR (Classic), safety-critical systems (ISO 26262), ADAS, BMS, power steering, radar systems, BLDC motors, UDS diagnostics, microcontroller bring-up, hypervisors, system optimization (memory & performance), hardware abstraction layers, test automation Tools: Trace32, Git, SVN, JIRA, Jenkins, CANoe, IBM DOORS, PTC, Code Collaborator, iSYSTEM IC5000/5700, Oscilloscopes, Signal Generators, Soldering Stations Tech: RP2040, STM32, Infineon Aurix, Renesas RH850, CAN/CAN-FD, I2C, SPI, RS232/RS485, USB, DMA, UWB, Ethernet Methodologies: Agile, MISRA-C, V-Model, unit testing, test-driven development, version-controlled build systems, modular software architecture, cross-functional team collaboration |
| DV | EUDV1 | 13+ | Romania | Skills: Pre-silicon verification, block- and top-level testbench development, constrained-random testing, coverage-driven verification, RTL emulation, FPGA programming, validation planning and reporting, requirement tracking, debugging and system integration, team training and onboarding
Languages: SystemVerilog, C, C#, Visual Basic, Python, Shell scripting Experience: 13 years in verification and validation (7 in digital verification, 6 in validation), UVM/OVM methodologies, sensor emulation (pressure/magnetic), microcontroller firmware (Microchip, Atmel, Texas Instruments, Infineon), protocol-level experience (AHB, I2C, SPI, UART, I2S, TDM, DFI, GDDR6, LPDDR5/4, HBM3, PSI5, DOCSIS 3.x) Tools: Cadence Incisive, Mentor ModelSim/Questa/RunManager, ClearCase, TortoiseSVN, JIRA, Perforce, FPGA dev tools Tech: UVM-compliant testbenches, firmware development for microcontrollers, sensor interfacing, continuous integration systems, FPGA-based emulation, aspect-oriented programming Methodologies: UVM, OVM, coverage-driven verification, Agile-style development, continuous integration, version control workflows |
| DV | EUDV2 | 12+ | Romania | Skills: Block-level, sub-system, and system-level verification; client collaboration (US, Israel, China); maintenance and support; protocol-level debugging; verification planning
Languages: SystemVerilog (12+ years), e/Specman, C, C++, Python, Perl, Bash, Shell scripting Experience: 7+ years in UVM-based verification, experience with eRM and VMM methodologies, protocol verification (Aurora 64b/66b, IEEE 802.11/802.3/802.1ah/802.1ad, PCIe, SPI, I2C, eMMC, AHB, APB) Tools: Cadence Incisive, Synopsys VCS/DVE, vManager, vPlanner, Perforce Tech: UVM, verification architecture across multiple design levels, protocol stack understanding, scripting for automation and tooling Methodologies: UVM (primary), eRM, VMM |
| DV | EUDV3 | 19+ | Romania | Skills: ASIC & SoC functional verification, testbench and VIP development, performance testing, compliance & stress testing, fast onboarding with minimal info, cross-company collaboration
Languages: SystemVerilog, SystemC, e/Specman, Vera, Verilog, C, C++, Perl, Bash Experience: 19+ years in chip development; block-level, top-level, black-box, gray-box, and white-box verification; protocols (Ethernet, IPv4/IPv6, TCP/UDP, IEEE1588, MPLS, TRILL, GPON, DOCSIS); coverage-driven and constrained-random verification Tools: Modelsim/Questa, Synopsys VCS/DVE, Cadence NC-sim, irun, vManager, Linux, CVS, ClearCase, Perforce, SVN, JIRA, Confluence Tech: Object-oriented and aspect-oriented programming, TLM modeling, cycle-accurate environments, performance checkers, Network Processor architecture Methodologies: RVM, VMM, UVM (flexible and improvement-oriented) |
| DV | EUDV4 | 7+ | Romania | Skills: Functional verification (random stimuli, coverage, black-box), UVM testbenches, fault injection, regression testing, safety mechanism validation, modeling & scoreboard integration, formal verification (basic), test documentation & reviews, full-stack web development
Languages: SystemVerilog, SystemC, Python, JavaScript, C#, NodeJS, React, SQL Tools: Xcelium, NCSim, Questasim, Cadence IMC, GitHub, GitLab, ClearCase, Perforce, JIRA, Confluence, Jasper (limited experience) Tech: Azure (AD, Sentinel), Postgres, regression pipelines, parameterized verification environments, UVC/SDK/architecture integration |
| DV | EUDV5 | 16 | Serbia | Skills: Team collaboration, fast learner, problem-solving in complex environments, debugging, functional verification (SystemVerilog, UVM, e-Language)
Languages: SystemVerilog, e-Language, Python, C, C++ Verification Tools: Cadence SimVision, vManager, vPlanner, Jasper Version Control: Git, SVN, Accurev Operating Systems: Windows, Linux |
| DV | EUDV6 | 12+ | France | Skills: Verification environment development, directed and random testing, functional coverage, system verification, IP model creation, regression testing, automation with scripting, log and wave analysis, safety-critical verification
Languages: VHDL, SystemVerilog (UVM), TCL, Bash, tcsh, C/C++, Assembly, Matlab, Python Experience: Development of UVM-based verification environments; script automation (Bash, TCL) to enhance test execution and result logging; coverage-driven verification; creation of verification IP models; functional and safety verification for aerospace systems Tools: Xilinx ISE, Vivado, Synopsis VCS, Verdi, QuestaSim, Git, ClearTool, Questa, Modelsim Tech: ARM Cortex A9, Texas Instruments DSP, Xilinx Zinq, Artix-7, ASICs, CAN, SPI, I2C protocols, safety-critical standards (DO-254 DAL-A), testbench development, directed and random test generation, assertion writing Methodologies: UVM, OOP, directed test, randomization, coverage analysis, log and wave analysis, regression testing, functional coverage improvement, FPGA-based verification |
| DV | EUDV7 | 7+ | Serbia | Skills: Digital verification, bug detection, problem-solving, verification plan development, test sequence and environment creation, coverage analysis, formal verification, regression cleaning, IP verification, protocol verification
Languages: SystemVerilog (UVM), Verilog, Perl, Python Experience: Over 6 years in digital verification; development of various verification environments for power management chips, scanners, and power supply chips; functional verification of protocols like I2C, EEPROM, and intra-chip communication; formal verification and regression cleaning; testbench and environment creation Tools: Verdi, Jasper Gold, SystemVerilog (UVM), Perl, Python Tech: Power management chips, EEPROM control, Type-C state machine, intra-chip communication, I2C protocol, real number model integration, AMS model comparison, digital output verification Methodologies: UVM, formal verification, coverage analysis, regression cleaning, test environment development, verification plan creation, test sequence development |
| DV | EUDV8 | 8+ | Serbia | Skills: IP/Top-level verification, verification plan writing, regression debugging, test sequence development, coverage analysis, block-level verification, top-level verification, protocol verification (AMBA, SPI, PRI, Ethernet), software debugging, environment development
Languages: SystemVerilog, Verilog, e language (Specman), Python, C, C++, Assembly Experience: Top-level verification for RDMA, RxH, DSP, SerDes, and memory systems; IP verification for automotive radar and autonomous driving chips; regression analysis and test plan writing; software and hardware integration testing; cross-functional team collaboration Tools: Synopsys VCS, Cadence Xcelium, Eclipse (DVT plugin), Kate, gedit, Perforce, SVN, GitHub, Polarion Tech: Functional verification, coverage-driven testing, regression automation, IP/SoC verification, software/debug integration Methodologies: UVM, random verification, eRM (e language), formal verification |
| DV | EUDV9 | 6+ | Serbia | Skills: Application software setup and configuration, test plan development, test environment setup, regression testing, functional and coverage verification, mixed C/SV environment integration, scoreboard implementation, assertions development
Languages: C, SystemVerilog, Python, GNU Make, Bash Tools: VCS, Verdi, Xcelium, vManager, simVision, Git Tech: UVM, EVL, memory verification, golden vector-based testing, functional and formal coverage analysis Methodologies: UVM, object-oriented programming (OOP), verification training in UVM methodology |
| DV | EUDV10 | 10 | Serbia | Skills: Functional verification plan development, UVM environment and uVC development, testbench creation, functional coverage implementation, basic formal verification, regression debugging, scripting for run-test and regression flows, register model instantiation
Languages: SystemVerilog, Verilog, SVA, E/Specman, C, C++, Java, SQL, Python, Perl Experience: IP design verification, SoC-level and formal verification Test case development, metric-driven random-constraint functional verification, and flow setup for test and regression UVM-based test development, including coverage implementation and maintaining regression flows Functional verification of IPs and SoC subsystems using UVM, E/Specman, and SystemVerilog assertions Tools: Cadence Xcelium, Mentor Questa, Cadence JasperGold, vManager, Perforce, Git Tech: AMBA AHB/APB, DDR4, AXI, Valens SIF (similar to USB3) Methodologies: UVM, functional and formal verification, object-oriented programming (OOP), metric-driven test development |
| DV | EUDV11 | 7 | Serbia | Skills: Digital SoC verification, top digital design verification, FPGA verification, embedded software design, full UVM testbench development, verification environment architecture, coverage and assertion definitions, reset-on-the-fly testing, RTL simulation and debugging
Languages: VHDL, SystemVerilog, Verilog, C, C++, Python, Git, SVN Tools: Cadence SimVision, Altera Quartus II, Altera ModelSim, Eclipse, Visual Studio, NetBeans, Verdi, vManager, Git, SVN, vPlan Tech: UVM methodology, RTL simulation, digital IP and SoC verification, RISC-V processor verification, automotive verification, battery management system verification Protocols Knowledge: AMBA APB, SPI, AHB, I2C, CAN Languages: English (Fluent), French (Basic) Degree: Final Year Student in Computer Engineering and Information Theory, Faculty of Electrical Engineering, University of Belgrade, Serbia |
| DV | EUDV12 | 4+ | Romania | Skills: UVM testbench development, SystemVerilog assertions (SVA), coverage planning and closure, protocol checkers, stimulus generation, cluster and top-level verification, regression debugging, training and mentorship, verification planning, block-level and top-level design verification, freelance consulting, automotive verification projectsLanguages: SystemVerilog, UVM, Verilog, VHDL, C++, C, SVATools: Questasim, Xcelium, Verdi, DVT Eclipse IDE, vManager, Perforce, Git, SVNTech: UVM methodology, automotive SoC verification, cluster-level and block-level verification, SPI Master protocol, parity and connectivity verification, PVT simulationsProtocols Knowledge: Wishbone, SPI, LPI, APB, AHB, I2COther Strengths: Strong communication, teamwork from professional handball career, time management, mentorship and training, quick learning in new environments |
| DV | EUDV13 | 19+ | UK | Skills: Digital SoC and IP verification, functional and subsystem verification, constrained-random verification, coverage-driven verification, assertion-based verification, safety verification (DFU), regression testing, reference model development, UVM testbench creation, feature extraction and verification planning, migration of environments (Specman to UVM), coverage closure, certitude fault analysis, debug of RTL and C-models, integration of VIPs, protocol checker implementation, data integrity check with scoreboards
Languages: SystemVerilog, Verilog, VHDL, Specman E-language, C, Python, Perl, Shell, Makefile, TCL, VBScript Tools: Cadence Xcelium, Synopsys VCS, ModelSim, Certitude, VManager, ClearCase, CVS, Perforce, Excel (automation), Eclipse, Visual Studio Tech: UVM methodology, eRM methodology, full chip and module-level verification, C-model integration, standalone and SoC environment setup, automation scripting, safety and fault injection testing Protocols Knowledge: AXI, AHB, OCP, PCI, JTAG, Ethernet, SERDES, I2C, internal protocols (VBUSM, RHEA, NoC) |
| Dft | DfTEU1 | 15+ | Germany | Skills: DfT architecture & implementation, scan insertion, MBIST, BSCAN, ATPG (stuck-at, transition, path delay, IDDQ), test compression, RTL design (Verilog/VHDL), SoC integration, silicon debug, failure analysis, post-silicon validation, pattern simulation, SDF simulation, timing closure, test plan development, team leadership (up to 20 engineers), yield improvement analysis, analog & digital DfT, TAP/JTAG scan stitchingLanguages: Verilog, VHDL, Shell scriptingTools: Synopsys DFT Compiler, ICC, PrimeTime, Mentor TestKompress, FastScan, Cadence Embedded Test, Atrenta Spyglass, ModelSim, VCS, NC-Sim, Lint tools, LVS/DRC tools Tech: SoC-level DfT, ATPG pattern generation, scan clock control integration, memory test debug, analog IO test, digital VISA debug, burn-in test, Schmoo plots, wafer probing, yield issue triage (65nm), IEEE 1149.x (BSCAN, TAP), P1500 compliance, MBIST & PBIST insertion Protocols Knowledge: JTAG, IEEE 1149.1/6, P1500, LoS, LoC |
| Dft | DfTEU2 | 5 | Germany | Skills: Scan insertion, ATPG (stuck-at, transition, path delay), DRC violation debugging, low test coverage analysis, MBIST simulation, zero-delay & timing simulations, JTAG protocol, pattern generation, pattern simulation, Verdi-based debug, collaborative and independent problem-solvingLanguages: Tcl, basic Linux scripting Tools: Siemens Tessent (Scan, TestKompress, FastScan), Synopsys VCS, Verdi, DVE, Cadence Xcelium Tech: RTL-level DfT, block-level scan insertion, fault simulation, zero delay & timing debug, coverage drop analysis, test point insertion, S1 & S2 DRC fixes, MBIST simulations Protocols Knowledge: JTAG (basic), IEEE fault models (stuck-at, transition, path delay) |
| Dft | DfTEU3 | 25+ | Germany | Skills: Design for Test (DfT) strategy, ATPG (stuck-at, transition, path delay, IDDQ), scan & MBIST/BSCAN insertion, silicon bring-up, gate/RTL-level simulation, test pattern compression, post-silicon debug, failure analysis, test automation, simulation planning, ISO certification leadership, DV environment setup, test plan execution, team mentoring, SoC test integration, simulation regression, DV methodology development, tester knowledgeLanguages: Tcl, Shell scripting, Verilog, VHDL Tools: EDA: Synopsys ICC, Design Compiler, DFT Compiler DFT-Specific: Mentor Tessent, FastScan Simulation & Debug: Verdi, VCS Automation & Environment: Custom regression environments, simulation infra Tech: SoC-level DfT implementation, analog DfT (PMIC), mobile processors, ISO 9001 process setup, AMS verification, diagnostic flow setup, zero delay & timing simulations, test chip design verification, production test flows, test coverage analysis |