RISC-V Verification, Zurich
RISC-V is rapidly transforming the semiconductor landscape with its open and extensible instruction set architecture. As adoption accelerates across industries, the need for robust and scalable verification methodologies has never been more critical.
Join us at DVClub Zurich as we dive into the latest innovations and challenges in RISC-V verification. This event will bring together leading experts to share real-world insights, best practices, and advanced techniques for verifying RISC-V cores and complex systems. Whether you’re building commercial RISC-V products or exploring open-source initiatives, this is a must-attend for anyone passionate about quality and reliability in hardware design.
Agenda (CEST)
| Time | Session Description | Presentations | Videos |
|---|---|---|---|
| 12.00 | Arrival, registration, networking, light refreshments | ||
| 13:00 | Derisking the RISC-V by Puneet Goel, Coverify | ||
| 13:30 | Advanced RISC-V Verification by Dave Kelf, Breker Systems | ||
| 14:00 | Extending a RISC-V Industrial-Grade Core (without breaking it) by Mike Thompson and Cairo Caplan, Open HW Group | ||
| 14:30 | Security verification of AXI on RISC-V by Melisande Zonta-Roudes, ETH Zurich | ||
| 15:00 | Break with refreshments/networking | ||
| 15:30 | Automatic ISA analysis for Secure Context Switching by Neelu Shivprakash Kalani, EPFL & IBM Research | ||
| 16:00 | Proof Strategies in the Comprehensive Formal Verification of the Ibex Processors by Louis-Emile Ploix, lowRISC / University of Oxford | ||
| 16:30 | Strengthening RISC-V with Formal Verification for your next tape out: Properties, Coverage, and Model Checking by Cristina Augello & Stefano Moncalvo, STMicroelectronics | ||
| 17:00 | MileSan: Detecting Exploitable Microarchitectural Leakage via Differential Hardware-Software Taint Tracking by Tobias Kovats, ETH Zurich | ||
| 17:15 | Pathfinder: Constructing Cycle-accurate Taint Graphs for Analyzing Information Flow Traces by Katharina Ceesay-Seitz, ETH Zurich | ||
| 17:30 | Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection by Matej Bölcskei, ETH Zurich | ||
| 17:45 | Refreshments/networking |
