FPGA Front Runner February 2025

View Video: https://youtu.be/0m81FOZ7LVM

View Blog: Techworks – FPGA Front Runner Event: A Glimpse into the Future of AI and FPGA Technologies

• Topic – Introduction to Renishaw
• Abstract –

• Topic – An Introduction to Techworks-AI
• Abstract – Following on from the successful launch of Techworks-AI at Bletchley Park in April 2024, with a focus on engineering the fundamentals of Trustworthy AI, Gareth will outline a new Techworks-AI community vision for 2025, bringing together members, regardless of sector of operation, who have a common interest in AI/ML technology, developments and applications, to create an exciting new ecosystem which will cross pollinate ideas and drive innovation.

• Topic – Automating the design of bespoke AI accelerator IP
• Abstract – FPGA devices are an exceptionally powerful platform for deploying Convolutional Neural Network (CNN) models in a wide range of settings, from embedded systems to data centers. The fine-grain configurability of FPGA devices affords them the ability to deploy highly customized accelerator However, discovering the optimal accelerator design for a specific CNN workload and objective is challenging given the vastness and complexity of the design space. This talk discusses the Heronic Toolchain, which makes use of streaming architecture components and automated design space exploration techniques to solve the optimization problem of mapping CNN devices to FPGAs. The talk will delve into the details of this toolchain and how it has been used to discover high-performance designs for applications such as Image Classification, Object Detection, and TinyML.

• Topic – Versatile Instruction Set Computing
• Abstract – Explaining a semiconductor core IP called VISC (Versatile Intrinsic Structured Computing). VISC is compatible with the standard RISC-V ISA and uses a compression and sequencing technology to enable entire algorithmic routines to be optimised for parallel execution. This can be used in chip from embedded microcontrollers to high- performance computing.

• Topic – Novel bio-inspired encryption using SNNs suitable for FPGA: A Privacy-Preserving Approach
• Abstract –Privacy concerns regarding confidential data processed on servers have highlighted the need for secure strategies. One promising solution is asymmetric encryption, which employs a pair of keys (public and private) to ensure secure communication without a shared key. This enables clients to securely use machine learning models owned by third parties via encrypted data transmission. To enhance efficiency and reduce power consumption, Spiking Neural Networks (SNNs) that mimic the human brain’s behaviour with sparse, dynamic, and event-driven processing have been utilised to encrypt and later decrypt files.
• We propose a bio-inspired encryption approach using custom SNNs to address technical challenges in encryption parameter selection and increase security. The approach is tailored for implementation on Field-Programmable Gate Arrays (FPGAs), leveraging their parallelism and low-power capabilities to enhance computational efficiency. FPGAs play a crucial role in this framework by providing a secure environment for storing private keys directly within the programming logic. Unlike traditional systems where keys might be stored in volatile memory or external storage, embedding private keys in FPGA logic significantly reduces the risk of unauthorised access or tampering. This hardware-level integration not only enhances security but also ensures faster cryptographic operations due to the close coupling of encryption algorithms with FPGA-optimised hardware. By combining the adaptability of FPGAs with the advanced features of SNNs, the proposed approach achieves a robust, efficient, and secure encryption solution suitable for modern data processing challenges.

• Topic – How to port AI systems to new computer architectures
• Abstract – If you have a novel computer architecture, or even just a specialist accelerator, how do you bring up standard AI systems such as TensorFlow and PyTorch to take best advantage of your processor or accelerator.
• In this talk we’ll look at the various approaches that can be used to bring up AI systems, whether for small embedded systems or large HPC accelerators. We will particularly look at a recent public project we carried out with Southampton University to bring up PyTorch on an AMD Zynq FPGA with a RISC-V softcore as AI accelerator over a 10 week period.

• Topic – AI in development and proto-typing for FPGA
• Abstract – Infra-structure free where distributed teams can design, verify, protype, and validate ASIC/FPGA anytime/anywhere is the wave of the future. In this talk, we provide a general overview of cloud for AI and simulation/verification. AI capabilities for ML/inference as well as F2 instance for FPGA prototyping is covered. Finally, we will cover our AWS Batch which gives you capability to run massive jobs for regression, gate level simulation, and place and route (P&R) in batch mode. All these capabilities allow for any organization to perform design/verification as well as prototyping on the AWS cloud today without any major capital or personnel to maintain the infrastructure on-premise. This setup helps with sustainability from a business point of view as well. Data sovereignty and security is covered.