Agenda (GMT)
| Time | Activity |
|---|---|
| 12:00 | Arrival, registration, networking |
| 13:00 | Semiconductor Education in VNUHCM-UIT: A Case Study with Design Verification Course Speaker: Minh Son Nguyen, Vietnam National University at HCM City – University of Information Technology |
| 13:30 | Agentic AI for Next-Generation Chip Verification: Verisium Powered by JedAI Speaker: Anika Sunda, Cadence Vietnam |
| 14:00 | Enhancing Verification Efficiency with AutoFocus on the Verisium Platform Speaker: Nguyen Hoang Nghia, Renesas Design Vietnam |
| 14:30 | Marvell’s Accelerated Infrastructure for AI Data Center Speaker: Quang-Dam Le, Marvell Technology Vietnam |
| 15:00 | Break with refreshments / networking |
| 15:30 | Unified Test Vector Framework Across Multiple Testbench Levels and Software Validation Speaker: Hung Le, BOS Semiconductors Vietnam |
| 16:30 | Practical Experience Sharing of Adopting Jasper on Register/Connection Verification Speaker: Richard An, Realtek Semiconductor Corp. |
| 17:00 | Using AI in Verification Speaker: Mike Bartley, Alpinum |
| 17:30 | END | Refreshments & Pizza / networking |
