Introduction to Semify’s Verification Revolution

According to Tchilikov, (2024), Semify is reshaping the landscape of hardware verification by integrating cutting-edge tools and methodologies. By leveraging Cocotb, a Python-based framework, they have streamlined the verification process, offering engineers a more straightforward, faster, and more effective way to verify modern hardware systems. This innovative approach enables engineers to efficiently test even the most complex designs, making hardware development more reliable and accessible.

Comprehensive Environment Setup

Tchilikov, (2024) explains that Semify meticulously designs its verification environment to cover every workflow aspect. It includes tools like Icarus Verilog for simulation, Cocotb for Python-driven testbenches, and GTKWave for waveform analysis. By seamlessly integrating these tools with Xilinx Vivado for FPGA programming, Semify provides a cohesive and efficient setup that supports robust verification from start to finish.

Simplified Module-Level Verification

Semify adopts a systematic approach to module-level verification, as highlighted by Tchilikov, (2024). By testing individual components like the OBI enslaver and Wishbone enslaved person on a unit level, they ensure reliability before integrating these modules into a more extensive system. This step-by-step method and directed tests written in Cocotb guarantee a thoroughly verified and cohesive design.

The Python Advantage in Verification

Python’s versatility makes it an ideal choice for verification tasks, as emphasized by Tchilikov, (2024). With Cocotb, engineers can utilize libraries like NumPy and SciPy to create golden models and debug complex designs. Python’s ability to handle advanced data structures, such as binary decision trees for cache controllers, simplifies the verification of intricate components while offering high-level insights into potential issues.

Balancing Benefits and Trade-offs

While Cocotb introduces a modern, Python-based approach to verification, there are a few trade-offs, such as slower simulation speeds and limited compatibility with some proprietary simulators, as mentioned by Tchilikov, (2024). However, the benefits far outweigh these drawbacks, offering tight integration into scripts, access to Python libraries, and a growing community-driven library of verification IP. Semify’s adoption of this methodology ensures a powerful and user-friendly solution for modern hardware verification challenges.

Note: For those interested in the latest advancements in verification technologies, the FPGA Verification Event 2025 (Verification Futures UK) offers an excellent opportunity to gain insights into cutting-edge verification practices.

References

Tchilikov,   C.    (2024).    Utilizing   COCOTB    for    efficient    functional    verification. https://www.semify-eda.com

Author

  • Mike Bartley

    Dr Mike Bartley has over 30 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams inside several companies (including STMicroelectronics, Infineon, Panasonic, and the start-up ClearSpeed) and also advised several companies on organisational verification strategies (ARM, NXP, and multiple start-ups). Mike successfully founded and grew a software test and hardware verification services company to 450+ engineers globally, delivering services and solutions to over 50+ clients in various technologies and industries. The company was acquired by Tessolve Semiconductors, a global company with 3000+ employees supporting clients in VLSI, silicon test and qualification, PCB, and embedded product development in multiple vertical industries. Mike is currently a Senior VP at Tessolve supporting VLSI globally, focusing on helping companies incorporate the latest verification techniques and strategies into their verification flows and building verification teams to support these companies in implementing them on IP and SoC projects. He is also responsible for the Tessolve Centres of Excellence running all R&D projects with Tessolve, including building a new AI capability across all Tessolve products and services. Mike has a PhD in Mathematics (Bristol University), and 9 MSc in various subjects including management (MBA), software engineering, computer security robotics and AI, corporate finance, and blockchain and digital currency. He is currently studying part-time for an MSc in quantum computing at the University of Sussex and the use of technology in healthcare at the University of Glasgow.

  • Mukul Kumar

    Design Verification (DV) Engineer at Tessolve Semiconductor with 3 years of semiconductor industry experience, specializing in UVM test benches, RTL design verification. Currently working in the Tessolve Centre of Excellence (CoE) on open-source RISCV projects (such as IBEX and PICOSOC) and on using AI to generate Portable Stimulus Standard (PSS) test benches from design specifications.