Introduction to Semify’s Verification Revolution

According to Tchilikov, (2024), Semify is reshaping the landscape of hardware verification by integrating cutting-edge tools and methodologies. By leveraging Cocotb, a Python-based framework, they have streamlined the verification process, offering engineers a more straightforward, faster, and more effective way to verify modern hardware systems. This innovative approach enables engineers to efficiently test even the most complex designs, making hardware development more reliable and accessible.

Comprehensive Environment Setup

Tchilikov, (2024) explains that Semify meticulously designs its verification environment to cover every workflow aspect. It includes tools like Icarus Verilog for simulation, Cocotb for Python-driven testbenches, and GTKWave for waveform analysis. By seamlessly integrating these tools with Xilinx Vivado for FPGA programming, Semify provides a cohesive and efficient setup that supports robust verification from start to finish.

Simplified Module-Level Verification

Semify adopts a systematic approach to module-level verification, as highlighted by Tchilikov, (2024). By testing individual components like the OBI enslaver and Wishbone enslaved person on a unit level, they ensure reliability before integrating these modules into a more extensive system. This step-by-step method and directed tests written in Cocotb guarantee a thoroughly verified and cohesive design.

The Python Advantage in Verification

Python’s versatility makes it an ideal choice for verification tasks, as emphasized by Tchilikov, (2024). With Cocotb, engineers can utilize libraries like NumPy and SciPy to create golden models and debug complex designs. Python’s ability to handle advanced data structures, such as binary decision trees for cache controllers, simplifies the verification of intricate components while offering high-level insights into potential issues.

Balancing Benefits and Trade-offs

While Cocotb introduces a modern, Python-based approach to verification, there are a few trade-offs, such as slower simulation speeds and limited compatibility with some proprietary simulators, as mentioned by Tchilikov, (2024). However, the benefits far outweigh these drawbacks, offering tight integration into scripts, access to Python libraries, and a growing community-driven library of verification IP. Semify’s adoption of this methodology ensures a powerful and user-friendly solution for modern hardware verification challenges.

Note: For those interested in the latest advancements in verification technologies, the FPGA Verification Event 2025 (Verification Futures UK) offers an excellent opportunity to gain insights into cutting-edge verification practices.

References

Tchilikov,   C.    (2024).    Utilizing   COCOTB    for    efficient    functional    verification. https://www.semify-eda.com

Author

  • Mike Bartley

    Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification. Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP. Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions:

    Alpinum AI provides tools and automations using Artificial Intelligence to help companies reduce development costs (by up to 90%!)

    Alpinum Services provides RTL to GDS VLSI services from nearshore and offshore centres in Vietnam, India, Egypt, Eastern Europe, Mexico and Costa Rica.

    Alpinum Consulting also provides strategic board level consultancy services, helping companies to grow.

    Alpinum training department provides self-paced, fully online training in System Verilog, UVM Introduction and Advanced, Formal Verification, DV methodologies for SV, UVM, VHDL and OSVVM and CPU/RISC-V.

    Alpinum Events organises a number of free-to-attend industry events

    You can contact Mike (mike@alpinumconsulting.com or +44 7796 307958) or book a meeting with Mike using Calendly (https://calendly.com/mike-alpinumconsulting).

  • Mukul Kumar

    Design Verification (DV) Engineer at Tessolve Semiconductor with 3 years of semiconductor industry experience, specializing in UVM test benches, RTL design verification. Currently working in the Tessolve Centre of Excellence (CoE) on open-source RISCV projects (such as IBEX and PICOSOC) and on using AI to generate Portable Stimulus Standard (PSS) test benches from design specifications.