FPGA Front Runner: Event Highlights

The event was held on 18th February 2025, bringing together industry leaders and AI and FPGA technologies experts. Eight speakers presented their insights on AI-driven FPGA development, machine learning acceleration, and novel cryptographic security solutions. The event focused on fostering innovation, collaboration, and knowledge sharing in the semiconductor and AI ecosystem. Participants engaged in discussions, sharing practical applications and advancements in their respective fields.

Introduction to Renishaw

Speaker: Pete Leonard (Renishaw)

Renishaw, a global leader in precision measurement systems, utilizes AI to enhance manufacturing efficiency, product quality, and research, as highlighted by Leonard, (2025). AI algorithms improve metrology, robotics, and industrial automation. Encoders are critical in precision alignment for X-ray systems and machine tool calibration. AI-driven quality control systems detect real-time trends and anomalies, reducing variability. The challenges lie in applying AI to manufacturing processes, requiring reliable data collection, verification, and validation.

An Introduction to Techworks-AI

Speaker: Gareth Richards (TechWorks)

TechWorks facilitates AI and FPGA innovation across multiple sectors, including semiconductors, autonomous platforms, and cybersecurity, according to Richards and TechWorks, (2025). The organization promotes collaboration between industry leaders, research institutions, and regulatory bodies. TechWorks ensures that AI applications in FPGA development remain cutting-edge by engaging in best practices, road mapping, and advocacy. They focus on advancing AI for UK deep-tech industries through networking, funding opportunities, and knowledge-sharing events.

Automating the Design of Bespoke AI Accelerator IP

Speaker: Petros Toupas (Heronic Technologies)

FPGA programmability allows for highly customized AI accelerators, as mentioned by Petros Toupas, (2025). However, challenges include vast design space, on-chip memory constraints, and inefficient use of resources. Heronic Technologies employs machine learning for design space exploration (DSE), optimizing performance, power, and area trade-offs. Techniques such as layer-level parallelism, parameter streaming, and sparsity exploitation ensure high efficiency. AI-driven automation aids in generating optimized FPGA hardware for deep learning workloads.

VISC – A Microprocessor Accelerator Architecture in FPGA

Speaker: James Lewis (RED Semiconductor)

VISC is a novel approach to AI acceleration, enhancing the efficiency of RISC-V architectures, as emphasized by Lewis, (2025). It optimizes execution by abstracting hardware complexities, allowing developers to focus on problem-solving rather than hardware constraints. Applications include edge AI, cryptography, and real-time data processing. FPGA-based functional verification ensures the viability of VISC for commercial adoption, with future transitions toward dedicated silicon solutions for large-scale deployments.

Novel Bio-Inspired Encryption Using SNNs Suitable for FPGA: A Privacy-Preserving Approach

Speaker: Dr. Pedro Machado (Nottingham Trent University)

This research explores Spiking Neural Networks (SNNs) for cryptographic security, leveraging event-driven computation and synaptic plasticity, as mentioned by Machado et al., (2025). The SNN model integrates RSA encryption, encoding, and decoding data through spike-timing mechanisms. FPGA implementations provide hardware acceleration, optimizing power efficiency for real-time encryption applications. Performance evaluation using Victor Purpura (VP) and Van Rossum (VR) metrics confirms encryption stability, with further improvements planned via hybrid quantum-resistant cryptography.

How to Port AI Systems to New Computer Architectures

Speaker: Jeremy Bennett (Embecosm)

This session outlines the transition of AI systems to novel computing architectures, emphasizing pre-silicon development, RISC-V optimizations, and AI-enabled microcontrollers, as highlighted by Bennett and Jones, (2025). OneAPI is leveraged for cross-platform portability, simplifying AI application deployment. Case studies on interposers and performance benchmarking highlight efficiency improvements, showcasing reduced execution time and enhanced throughput in FPGA-based AI accelerators.

Realising the Enormous Potential of FPGAs for Machine Learning

Speaker: Giles Peckham (Myrtle Software)

Myrtle.ai optimizes machine learning inference on FPGAs, offering ultra-low latency and high energy efficiency, as mentioned by Peckham, (2025). Their VOLLO framework allows ML developers to seamlessly design, evaluate, and deploy AI models. Compared to GPUs, FPGA solutions provide superior real-time inference for applications like financial trading, network security, and telecommunications. Future advancements will include support for larger models, expanded FPGA families, and reduced latency.

AI in Development and Proto Typing for FPGA

Speaker: Mark Azadpour (Amazon Web Services)

This presentation discusses the role of AI and cloud computing in functional verification, particularly in ASIC and FPGA design, according to Azadpour and Amazon Web Services, Inc., (2024). Verification takes significant project time, and teams can leverage the cloud for AI-driven automation, perform regression runs, and create generative test cases. Amazon SageMaker provides an integrated data and AI development environment, helping teams scale AI use cases efficiently while maintaining security and compliance. AWS FPGA developer AMI and batch processing tools enable parallel execution of simulations, reducing verification bottlenecks.

Summary

The FPGA Front Runner 2025 event provided valuable insights into the latest advancements in AI and FPGA technologies. Industry experts explored innovations in AI-driven FPGA development, cryptographic security, and machine learning acceleration. Discussions emphasized practical applications, emerging trends, and the growing role of AI in FPGA-based solutions. The event reinforced the importance of collaboration and knowledge sharing in shaping the future of AI and semiconductor industries.

Note: For those interested in the latest advancements in verification technologies, the FPGA Verification Event 2025 (Verification Futures UK) offers an excellent opportunity to gain insights into cutting-edge verification practices.

References

Leonard, P. (2025). Renishaw – A brief introduction and update of products, and the use of AI technology and challenges.

Richards, G. & TechWorks. (2025). FPGA Front Runner. In TechWorks ecosystem.

Petros Toupas. (2025). Future of AI & semiconductors. In Heronic Technologies.

Lewis, J. (2025). VISC – Versatile Intrinsic Structured Computing. https://redsemiconductor.com/

Machado, P., Pulivathi, M., Oikonomou, A., & Ihianle, I. K. (2025). Novel bio-inspired encryption using SNNs suitable for FPGA: A Privacy-Preserving Approach. Nottingham Trent University.

Bennett, J., & Jones, W. (2025). How to port AI systems to new computer architectures. Embecosm. https://embecosm.com

Peckham, G. (2025). Realising the enormous potential of FPGAs for machine learning.

Azadpour, M. & Amazon Web Services, Inc. (2024). AI based functional verification in the cloud. Amazon Web Services, Inc. https://aws.amazon.com/batch/

Author

  • Mike Bartley Tessolve

    Dr. Mike Bartley, Senior Vice President, Tessolve Mike is responsible for VLSI sales for Europe as well as supporting Design Verification (DV) sales globally. Mike has 30+ years DV experience and has built and managed state-of-the-art DV teams inside several companies (including STMicroelectronics, Infineon, Panasonic, and the start-up ClearSpeed) and also advised several companies on organisational DV strategies (ARM, NXP, and multiple start-ups). Mike successfully founded and grew a DV services company to 450+ engineers globally, delivering services and solutions to over 50+ clients in various technologies and industries. The company was acquired by Tessolve Semiconductors in 2020. Mike also manages the Centre of Excellence (CoE) activities at Tessolve. This includes building new products and services across all of the Tessolve business units (BU): VLSI, Silicon Test, PCB and embedded SW and products. The CoE is also developing AI capabilities and expertise across Tessolve. This is used to improve efficiencies across all the internal divisions (finance, HR, recruitment, procurement, program management, etc) as well as efficiencies and new services across the BU.