Staffing Solutions – USA
| Domain | Code | Years | Country | Main skills |
| DV | USDV1 | 15+ | USA | Expertise: SoC/ASIC Verification, UVM Methodology Languages/Tools: SystemVerilog, SVA, Python, Perl, C Verification Methods: Constrained-Random Verification (CRV), Coverage-Driven Verification Tools: VCS, DVE, Verdi, QuestaSim, ModelSim, Xcelium Protocols & Interfaces: AMBA (AXI, AHB, APB), I²C System-Level Skills: SoC architecture, IP/subsystem integration, DSP fundamentals, Mixed-Signal Verification Debug: GLS, Waveform analysis, Coverage closure |
| DV | USDV2 | 5+ | USA | Expertise: RTL Design & Verification, SoC-Level Testbenches Languages/Tools: Verilog, SystemVerilog, Assembly (CASM), Python, C Verification Methodologies: UVM, OVM Protocols: PCIe Gen 4, AMBA (APB, AHB), DDR Tools: Cadence Xcelium, Synopsys VCS/DVE/Verdi, Mentor QuestaSim, Xilinx ISE OS Experience: Windows, Linux, Unix Highlights: SV-UVM testbench development, UVM RAL, assertion-based verification, constraint randomization, functional/code coverage System Design: DDR, cache systems, branch prediction, instruction pipelining, ISA-level understanding |
| DV | USDV3 | 12+ | USA | Expertise: Emulation & SoC/FPGA Verification Specialties: Emulation flow setup, FPGA library mapping, debug & root-cause analysis Verification Methodologies: UVM-based test development, sequence creation, functional coverage enhancement Experience: IP/SoC regression testing, silicon-vs-emulation debug, identifying hardware/environment issues Strengths: Time-constrained problem solving, cross-functional debug, efficient failure analysis in emulated environments |
| DV | USADV4 | 12+ | USA | Skills: Emulation setup from simulation databases, FPGA library mapping, emulation flow bring-up, IP/SoC verification regressions, root-cause debug under time constraints, silicon vs. emulation issue identification, UVM-based test case and sequence development, functional coverage improvement
Languages: Verilog, SystemVerilog, Python, C, C++ Experience: Emulation and prototyping with Zebu, Veloce, and HAPS; protocol-level testing for MIPI (DSI), I2C, SPI, AHB, UART; testbench and environment debugging; cross-functional engineering collaboration Tools: Zebu, Veloce, HAPS, Git, Jira, Jasper, Cadence SimVision, vManager, vPlanner, SVN, Accurev, Linux, Unix, Windows Tech: Functional and formal verification, coverage-driven testing, testbench bring-up, regression automation, hardware/software integration Methodologies: UVM, Formal Verification |
| DV | USADV5 | 3 | USA | Skills: SoC top-level verification, UVM-based testbench development, AXI/SPI/Ethernet protocol debugging, boundary scan (IEEE 1149.1) verification, PLL block verification, regression failure analysis, functional coverage and assertions, test planning and execution, JIRA handling, Perforce repository usage
Languages: SystemVerilog, Verilog Tools: Linux, Perforce, JIRA Tech: UVM methodology, SoC-level environment, AXI protocol verification, PLL clock path validation, Ethernet MAC testing, boundary-scan (JTAG) interface, APB interface, interrupt condition verification, CRC and data path integrity Protocols Knowledge: AXI, SPI, Ethernet, JTAG (Boundary Scan) |