Staffing Solutions – India
| Domain | Code | Years | Country | Main skills |
| DV | DV1 | 5+ | India | Skills: RTL Design, SV-UVM testbench, System Verilog assertions Languages: Verilog, System Verilog, C, Assembly Scripting: Python Protocols: PCIe Gen 4, AMBA (APB, AHB), DDR Tools: Xcelium, VCS, DVE, Verdi, Questa, Xilinx-ISE Key Strengths: Integration, verification plan, functional coverage |
| DV | DV2 | 5+ | India | “Skills: FPGA/ASIC design and verification, digital signal processing, secure communication systems, RF system integration, timing analysis, lab debugging, test planning, power/performance optimization, system-level integration
Languages: Verilog, VHDL, C, C++, MATLAB Experience: 5+ years in FPGA design across research, academic, and corporate projects; strong background in SDR and cryptographic hardware; hands-on lab debugging and signal analysis; end-to-end digital design implementation from RTL to synthesis and verification Tools: Vivado, ModelSim, MATLAB/Simulink, Xilinx ISE, PicoZed, SODAQ, AD9361 Tech: SDR, RF systems, NB-IoT, secure baseband communication, ADC/FFT implementation, FPGA bring-up and testing, embedded signal processing Methodologies: Structured test planning, FPGA prototyping, HDL driver customization, simulation and lab-based validation, performance tuning for power-sensitive applications” |
| Dft | Dfteng-1 | 13+ | India | Skills: Fault modeling, Fault simulation, Fault collapsing, Scan chain insertion Languages: Verilog, System Verilog, C, C++, Python, TCL Experience: Scan insertion, BIST/MBIST insertion, Test coverage improvement Tools: Xcelium, Synopsys VCS, DVE, Verdi, Questa Methodologies: UVM, OVM Protocols: PCIe Gen4, AMBA, DDR |
| Dft | Dfteng-2 | 5.5+ | India | Skills: Integrating DFT solutions, ATE testing, Scan design Experience: Expertise in BSCAN, scan insertion, optimizing silicon yield Tools: Tessent, Synopsys tools Key Achievements: Successful execution on Intel products |
| Dft | Dfteng-3 | 5 | India | Experience: in multiple technology nodes with automotive and AI applications Skills: DFT tools and flow, scan insertion, BIST, MBIST, ATPG Key Strengths: Leadership, training juniors, strong fundamentals in DFT and ASIC cycles |
| Dft | Dfteng-4 | 4+ | India | Skills: Scan insertion, IJTAG, MBIST, ATPG, Test coverage analysis Experience: Simulation debug, working with major EDA tools (Synopsys, Cadence, Mentor) |
| Dft | Dfteng-5 | 6 | India | Skills: Modus ATPG, Xcelium simulations, Tessent MBIST validation Tools: Spyglass, Tessent tools Scripting: Bash, TCL |
| Dft | Dfteng-6 | 3 | India | Skills: Fault modeling, Scan chain insertion, BIST/MBIST analysis Tools: Tessent FastScan, TestKompress, BoundaryScan Experience: Test coverage improvement, Fault simulation, DRC analysis |
| Dft | Dfteng-7 | 8+ | India | Skills: Block-level and full-chip DFT, Synthesis, Low pin scan implementation Experience: Experience in RTL writing and SDC writing |
| Dft | Dfteng-8 | 19+ | India | Skills: End-to-end DFT architecture, Test coverage analysis, Flow development Experience: Team leadership (15-20 members), silicon debug, DoE, RMA closures |
| Dft | Dfteng-9 | 3+ | India | Skills: Fault modeling, Scan chain insertion, BIST/MBIST insertion, ATPG Tools: Tessent FastScan, TestKompress, BoundaryScan Experience: DRC analysis, Test coverage improvement |
| Dft | Dfteng-10 | 11+ | India | Skills: ATPG for SAF, TR mode, Scan insertion, Memory BIST insertion Experience: Functional pattern validation, Simulation debug (Verdi/DVE), IP test vectors Tools: Synopsys/Mentor DFT flow, Formal Property check tools |
| Dft | Dfteng-11 | 4.5+ | India | Skills: DRC analysis, ATPG pattern generation, Scan debugging, Boundary Scan Experience: ROM/Memory validation, Post-silicon debugging |
| Dft | Dfteng-12 | 3 | India | Skills: Fault modeling, Scan chain insertion, BIST/MBIST insertion Tools: Tessent FastScan, TestKompress, BoundaryScan Experience: ATPG pattern generation, Test coverage improvement |
| Dft | Dfteng-13 | 3 | India | Skills: Fault modeling, Scan insertion, BIST/MBIST insertion Tools: Tessent FastScan, TestKompress, BoundaryScan Experience: Fault simulation, Test coverage improvement, RTL/Verilog coding |
| Dft | Dfteng-14 | 4 | India | Skills: IOTEST, UDR instructions, Static/Dynamic fault coverage Experience: Test coverage analysis, IOTEST framework implementation |
| Dft | Dfteng-15 | 8+ | India | Skills: MBIST Insertion, Pattern generation, Test validation Experience: Pre and post-silicon debug, ATPG DRC cleanup Tools: Synopsys, Mentor DFT tools |
| Dft | Dfteng-16 | 10 | India | Skills: Scan Insertion, ATPG, PBIST, Simulations Experience: Using tools like DFTCompiler, DFTMAX, Tetramax, Modus Tools: Xcelium, Verdi, VCS |
| Dft | Dfteng-17 | 12+ | India | Skills: DFT using Synopsys tools, Hardware/Software integration testing Experience: Testing in medical, avionics, automation sectors Tools: NI LabVIEW, Cadence Allegro, Mentor Graphics Protocols: UART, RS-232, RS-485, USB, I2C/SPI |
| Dft | Dfteng-18 | 5+ | India | Skills: DFT Implementation, Scan Insertion, BSCAN Experience: Pre-Si & Post-Si validation, Test Automation Tools: Synopsys Tetramax, TestKompress, VCS Scripting: Python, TCL, Shell |
| Dft | Dfteng-19 | 3+ | India | Skills: Test strategies, fault simulation, test coverage optimization Experience: Contributing to ASIC designs, collaborating with cross-functional teams |
| Dft | InfTeng1 | 4 | India | Skills: Advanced DFT methodologies (MBIST, LBIST, ATPG, Scan, BSCAN), SoC architecture design, RTL-to-GL synthesis, ATE debug, static timing analysis (STA), logic equivalence checking (LEC), gate-level simulation (GLS), design automation and scripting
Languages: Verilog, SystemVerilog, Python, Perl Experience: Design-for-Test implementation and debug across complex SoC designs; synthesis and STA using industry-standard tools; automation and efficiency improvement through scripting; test coverage enhancement for robust silicon validation Tools: Tessent (Siemens), Tetramax (Synopsys), Genus, DesignCompiler, QuestaSim, VCS, PrimeTime, Verdi, Visio, LEC Tech: MBIST, LBIST, ATPG, RTL/GL design and verification, Linux/Unix environments, RTL debug, ATE bring-up Methodologies: Structured DFT planning, Scan Insertion, Clock Domain Crossing, STA/LEC closure, GLS validation |
| DV | DV3 | 13 | India | Skills: ASIC and FPGA verification, UVM-based testbench development, constrained-random and coverage-driven verification, functional and code coverage closure, debug and regression handling, SCAN chain verification, DSP and CPU mailbox validation, test plan creation, scoreboard design, reusable verification infrastructure, RTL and gate-level simulations, Verilog-to-C model conversion, DFT methodologies, system-level integration, team leadership and mentoring
Languages: SystemVerilog, Verilog, Specman e, C, Shell, TCL Tools: Cadence NCSim, Synopsys VCS, Synopsys Verdi, Cadence eManager, GIT, ClearCase, Eclipse, Windows, Linux Tech: UVM methodology, ASIC & FPGA verification, Ethernet MAC (10G–100G), DSP data path testing, SCAN/DFT verification, JTAG, DMA, DOCSIS, transceiver IPs, mailbox communication protocols, RTL/gate-level simulation, IP and SoC level testing, verification IP integration Protocols Knowledge: UCIe, Ethernet, JTAG, DMA, DOCSIS, MAC Layer, APAX, Prism |
| DV | DV4 | 5.5 | India | Skills: ASIC/SoC verification, UVM-based testbench development, protocol validation (AXI, AHB, APB, PCIe, UART), constrained-random testing, functional and assertion coverage closure, RTL and GLS simulation, reusable VIP creation, test plan creation, debug and bug tracking, embedded systems development, subsystem-level verification, cross-functional team collaboration
Languages: SystemVerilog, Verilog, C, C++, Python, Shell, Perl Tools: Synopsys VCS, Cadence Xcelium, Verdi, Perforce, Linux, Windows Tech: UVM methodology, AXI4, PCIe Gen1–Gen5, UART, I2C, SPI, AHB3, timer IPs (GPT, WDT), embedded controller platforms (NXP, STM), biometric & security systems, VIP architecture, boundary constraint writing, RTL/gate-level testbench design Protocols Knowledge: AXI4, PCIe Gen1–5, UART, I2C, SPI, AHB3, APB |
| DV | DV5 | 3.5 | India | Skills: IP/SoC verification, UVM-based testbench development, functional and assertion coverage closure, test plan creation, debugging, system-level test case development, verification planning, lab enablement, legacy feature validation, SV-to-C and SV-to-VBA code conversion, Ethernet VIP review, training and onboarding support
Languages: SystemVerilog, Verilog, C, VBA Tools: Cadence Xcelium, Mentor Questasim, Cadence IMC, Cadence Vmanager, Linux Tech: UVM methodology, memory subsystem verification, Matrix_RevB ASIC, DRV_PATH feature development, Ethernet VIP, lab integration, ATE tool support, code cleanup and maintainability, verification IP understanding Protocols Knowledge: AXI4, Ethernet |
| DV | DV6 | 3.5 | Bangalore, India | Skills: UVM-based verification, RTL design & synthesis, testbench development, functional and code coverage analysis, assertion-based verification, simulation debugging, class-based verification environment development, protocol verification (AMBA), collaborative and independent problem-solvingLanguages: SystemVerilog, Verilog, basic Perl scriptingTools: Synopsys VCS, Questa Sim, ModelSim, Quartus PrimeTech: RTL-level design and verification, block-level testbench architecture, functional simulation, coverage closure (code + functional), class-based UVM environment, AMBA protocol-based verification, synthesis flow with Quartus Protocols Knowledge: |
| DV | DV7 | 3.5 | Bangalore, India | Skills: UVM-based testbench development, constrained-random test generation, functional and code coverage closure, protocol compliance verification, assertion and scoreboard implementation, regression debug, simulation log and waveform analysis, collaborative and independent problem-solvingLanguages: SystemVerilog, VerilogTools: Synopsys VCS, ModelSim, QuestaSim, Verdi Tech: Protocols Knowledge: |
| DV | DV8 | 5 | Bangalore, India | Skills: UVM-based testbench development, constrained-random test generation, functional and code coverage closure, protocol compliance verification, assertion and checker implementation, regression debugging, simulation log and waveform analysis (Verdi), emulation and simulation flow (Zebu, HAPS), register layer integration, verification planning and documentation, collaborative and independent problem-solvingLanguages: SystemVerilog, Verilog Tools: Tech: Protocols Knowledge: |
| DV | DV9 | 4 | Bangalore, India | Skills: UVM-based testbench development, constrained-random test generation, functional and code coverage analysis, VIP and IP integration, protocol compliance verification, reference model implementation, scoreboard/checker design, regression testing and debug, documentation of verification plans and results, visual quality and bit-accuracy verification, synthesizability optimization, proactive issue resolutionLanguages: SystemVerilog, Verilog Tools: Tech: Protocols Knowledge: |
| DV | DV10 | 3 | Bangalore, India | Skills: UVM-based testbench development, constrained-random test generation, functional and code coverage analysis, UART/SPI/I2C protocol verification, AON block and AI microcontroller verification, sensor fusion and wakeup-word signal validation, assertion-based verification, scoreboard/checker design, RTL-level debugging, FSM-based design, regression testing and debug, verification documentation and process improvementLanguages: SystemVerilog, Verilog, C, Shell Scripting Tools: Tech: Protocols Knowledge: |
| DV | DV11 | 2.6 | Bangalore, India | Skills: UVM-based testbench development, testplan creation, constrained-random test generation, functional coverage development and analysis, SVA-based assertion checks, protocol verification for AXI/APB/UCIe, regression testing using VManager, scoreboard/checker design, RTL-level debugging, lane repair and shift feature verification, reusable UVM component creation (driver, monitor, sequencer), sequence and scenario development, FIFO and SoC-level bus verificationLanguages: SystemVerilog, Verilog, C, Python Tools: Tech: Protocols Knowledge: |
| DV | DV12 | 2 | Bangalore, India | Skills: UVM-based testbench development, constrained-random test generation, coverage-driven verification, functional coverage analysis, assertion-based verification using SVA, scoreboard design, RTL-level debugging, regression testing using VManager, IP and sub-block level verification, lane repair feature verification in UCIe, MMPL resolution and PHY retrain scenario validation, FIFO and RAM verificationLanguages: SystemVerilog, Verilog, C, Python Tools: Tech: Protocols Knowledge: |
| DV | DV13 | 5.6 | Bangalore, India | Skills: UVM testbench development, constrained-random verification, functional and code coverage analysis, assertion-based verification (SVA), scoreboard and checker creation, regression testing, debug and root cause analysis, test scenario design, VIP integration, DPI interface development, protocol verification, code review, coverage-driven verification, RTL issue debuggingLanguages: SystemVerilog, UVM, C/C++, SVA, TCL, PERL (basic knowledge), Linux shell, Vim Tools: Tech: Protocols Knowledge: |
| DV | DV14 | 3 | Bangalore, India | Skills: UVM testbench development, constrained-random verification, functional and code coverage analysis, assertion-based verification (SVA), scoreboard and checker creation, regression testing, debug and root cause analysis, test scenario design, VIP integration, DPI interface development, protocol verification, code review, coverage-driven verification, RTL issue debuggingLanguages: SystemVerilog, UVM, C/C++, SVA, TCL, PERL (basic knowledge), Linux shell, Vim Tools: Tech: Protocols Knowledge: |