Staffing Solutions – India

DomainCodeYearsCountryMain skills
DVDV15+IndiaSkills: RTL Design, SV-UVM testbench, System Verilog assertions
Languages: Verilog, System Verilog, C, Assembly
Scripting: Python
Protocols: PCIe Gen 4, AMBA (APB, AHB), DDR
Tools: Xcelium, VCS, DVE, Verdi, Questa, Xilinx-ISE
Key Strengths: Integration, verification plan, functional coverage
DVDV25+India“Skills: FPGA/ASIC design and verification, digital signal processing, secure communication systems, RF system integration, timing analysis, lab debugging, test planning, power/performance optimization, system-level integration

Languages: Verilog, VHDL, C, C++, MATLAB

Experience: 5+ years in FPGA design across research, academic, and corporate projects; strong background in SDR and cryptographic hardware; hands-on lab debugging and signal analysis; end-to-end digital design implementation from RTL to synthesis and verification

Tools: Vivado, ModelSim, MATLAB/Simulink, Xilinx ISE, PicoZed, SODAQ, AD9361

Tech: SDR, RF systems, NB-IoT, secure baseband communication, ADC/FFT implementation, FPGA bring-up and testing, embedded signal processing

Methodologies: Structured test planning, FPGA prototyping, HDL driver customization, simulation and lab-based validation, performance tuning for power-sensitive applications”

DftDfteng-113+IndiaSkills: Fault modeling, Fault simulation, Fault collapsing, Scan chain insertion
Languages: Verilog, System Verilog, C, C++, Python, TCL
Experience: Scan insertion, BIST/MBIST insertion, Test coverage improvement
Tools: Xcelium, Synopsys VCS, DVE, Verdi, Questa
Methodologies: UVM, OVM
Protocols: PCIe Gen4, AMBA, DDR
DftDfteng-25.5+IndiaSkills: Integrating DFT solutions, ATE testing, Scan design
Experience: Expertise in BSCAN, scan insertion, optimizing silicon yield
Tools: Tessent, Synopsys tools
Key Achievements: Successful execution on Intel products
DftDfteng-35IndiaExperience: in multiple technology nodes with automotive and AI applications
Skills: DFT tools and flow, scan insertion, BIST, MBIST, ATPG
Key Strengths: Leadership, training juniors, strong fundamentals in DFT and ASIC cycles
DftDfteng-44+IndiaSkills: Scan insertion, IJTAG, MBIST, ATPG, Test coverage analysis
Experience: Simulation debug, working with major EDA tools (Synopsys, Cadence, Mentor)
DftDfteng-56IndiaSkills: Modus ATPG, Xcelium simulations, Tessent MBIST validation
Tools: Spyglass, Tessent tools
Scripting: Bash, TCL
DftDfteng-63IndiaSkills: Fault modeling, Scan chain insertion, BIST/MBIST analysis
Tools: Tessent FastScan, TestKompress, BoundaryScan
Experience: Test coverage improvement, Fault simulation, DRC analysis
DftDfteng-78+IndiaSkills: Block-level and full-chip DFT, Synthesis, Low pin scan implementation
Experience: Experience in RTL writing and SDC writing
DftDfteng-819+IndiaSkills: End-to-end DFT architecture, Test coverage analysis, Flow development
Experience: Team leadership (15-20 members), silicon debug, DoE, RMA closures
DftDfteng-93+IndiaSkills: Fault modeling, Scan chain insertion, BIST/MBIST insertion, ATPG
Tools: Tessent FastScan, TestKompress, BoundaryScan
Experience: DRC analysis, Test coverage improvement
DftDfteng-1011+IndiaSkills: ATPG for SAF, TR mode, Scan insertion, Memory BIST insertion
Experience: Functional pattern validation, Simulation debug (Verdi/DVE), IP test vectors
Tools: Synopsys/Mentor DFT flow, Formal Property check tools
DftDfteng-114.5+IndiaSkills: DRC analysis, ATPG pattern generation, Scan debugging, Boundary Scan
Experience: ROM/Memory validation, Post-silicon debugging
DftDfteng-123IndiaSkills: Fault modeling, Scan chain insertion, BIST/MBIST insertion
Tools: Tessent FastScan, TestKompress, BoundaryScan
Experience: ATPG pattern generation, Test coverage improvement
DftDfteng-133IndiaSkills: Fault modeling, Scan insertion, BIST/MBIST insertion
Tools: Tessent FastScan, TestKompress, BoundaryScan
Experience: Fault simulation, Test coverage improvement, RTL/Verilog coding
DftDfteng-144IndiaSkills: IOTEST, UDR instructions, Static/Dynamic fault coverage
Experience: Test coverage analysis, IOTEST framework implementation
DftDfteng-158+IndiaSkills: MBIST Insertion, Pattern generation, Test validation
Experience: Pre and post-silicon debug, ATPG DRC cleanup
Tools: Synopsys, Mentor DFT tools
DftDfteng-1610IndiaSkills: Scan Insertion, ATPG, PBIST, Simulations
Experience: Using tools like DFTCompiler, DFTMAX, Tetramax, Modus
Tools: Xcelium, Verdi, VCS
DftDfteng-1712+IndiaSkills: DFT using Synopsys tools, Hardware/Software integration testing
Experience: Testing in medical, avionics, automation sectors
Tools: NI LabVIEW, Cadence Allegro, Mentor Graphics
Protocols: UART, RS-232, RS-485, USB, I2C/SPI
DftDfteng-185+IndiaSkills: DFT Implementation, Scan Insertion, BSCAN
Experience: Pre-Si & Post-Si validation, Test Automation
Tools: Synopsys Tetramax, TestKompress, VCS
Scripting: Python, TCL, Shell
DftDfteng-193+IndiaSkills: Test strategies, fault simulation, test coverage optimization
Experience: Contributing to ASIC designs, collaborating with cross-functional teams
DftInfTeng14IndiaSkills: Advanced DFT methodologies (MBIST, LBIST, ATPG, Scan, BSCAN), SoC architecture design, RTL-to-GL synthesis, ATE debug, static timing analysis (STA), logic equivalence checking (LEC), gate-level simulation (GLS), design automation and scripting

Languages: Verilog, SystemVerilog, Python, Perl

Experience: Design-for-Test implementation and debug across complex SoC designs; synthesis and STA using industry-standard tools; automation and efficiency improvement through scripting; test coverage enhancement for robust silicon validation

Tools: Tessent (Siemens), Tetramax (Synopsys), Genus, DesignCompiler, QuestaSim, VCS, PrimeTime, Verdi, Visio, LEC

Tech: MBIST, LBIST, ATPG, RTL/GL design and verification, Linux/Unix environments, RTL debug, ATE bring-up

Methodologies: Structured DFT planning, Scan Insertion, Clock Domain Crossing, STA/LEC closure, GLS validation

DVDV313IndiaSkills: ASIC and FPGA verification, UVM-based testbench development, constrained-random and coverage-driven verification, functional and code coverage closure, debug and regression handling, SCAN chain verification, DSP and CPU mailbox validation, test plan creation, scoreboard design, reusable verification infrastructure, RTL and gate-level simulations, Verilog-to-C model conversion, DFT methodologies, system-level integration, team leadership and mentoring

Languages: SystemVerilog, Verilog, Specman e, C, Shell, TCL

Tools: Cadence NCSim, Synopsys VCS, Synopsys Verdi, Cadence eManager, GIT, ClearCase, Eclipse, Windows, Linux

Tech: UVM methodology, ASIC & FPGA verification, Ethernet MAC (10G–100G), DSP data path testing, SCAN/DFT verification, JTAG, DMA, DOCSIS, transceiver IPs, mailbox communication protocols, RTL/gate-level simulation, IP and SoC level testing, verification IP integration

Protocols Knowledge: UCIe, Ethernet, JTAG, DMA, DOCSIS, MAC Layer, APAX, Prism

DVDV45.5IndiaSkills: ASIC/SoC verification, UVM-based testbench development, protocol validation (AXI, AHB, APB, PCIe, UART), constrained-random testing, functional and assertion coverage closure, RTL and GLS simulation, reusable VIP creation, test plan creation, debug and bug tracking, embedded systems development, subsystem-level verification, cross-functional team collaboration

Languages: SystemVerilog, Verilog, C, C++, Python, Shell, Perl

Tools: Synopsys VCS, Cadence Xcelium, Verdi, Perforce, Linux, Windows

Tech: UVM methodology, AXI4, PCIe Gen1–Gen5, UART, I2C, SPI, AHB3, timer IPs (GPT, WDT), embedded controller platforms (NXP, STM), biometric & security systems, VIP architecture, boundary constraint writing, RTL/gate-level testbench design

Protocols Knowledge: AXI4, PCIe Gen1–5, UART, I2C, SPI, AHB3, APB

DVDV53.5IndiaSkills: IP/SoC verification, UVM-based testbench development, functional and assertion coverage closure, test plan creation, debugging, system-level test case development, verification planning, lab enablement, legacy feature validation, SV-to-C and SV-to-VBA code conversion, Ethernet VIP review, training and onboarding support

Languages: SystemVerilog, Verilog, C, VBA

Tools: Cadence Xcelium, Mentor Questasim, Cadence IMC, Cadence Vmanager, Linux

Tech: UVM methodology, memory subsystem verification, Matrix_RevB ASIC, DRV_PATH feature development, Ethernet VIP, lab integration, ATE tool support, code cleanup and maintainability, verification IP understanding

Protocols Knowledge: AXI4, Ethernet

DVDV63.5Bangalore, IndiaSkills:
UVM-based verification, RTL design & synthesis, testbench development, functional and code coverage analysis, assertion-based verification, simulation debugging, class-based verification environment development, protocol verification (AMBA), collaborative and independent problem-solvingLanguages:
SystemVerilog, Verilog, basic Perl scriptingTools:
Synopsys VCS, Questa Sim, ModelSim, Quartus PrimeTech:
RTL-level design and verification, block-level testbench architecture, functional simulation, coverage closure (code + functional), class-based UVM environment, AMBA protocol-based verification, synthesis flow with QuartusProtocols Knowledge:
AMBA (AHB2APB)
DVDV73.5Bangalore, IndiaSkills:
UVM-based testbench development, constrained-random test generation, functional and code coverage closure, protocol compliance verification, assertion and scoreboard implementation, regression debug, simulation log and waveform analysis, collaborative and independent problem-solvingLanguages:
SystemVerilog, VerilogTools:
Synopsys VCS, ModelSim, QuestaSim, VerdiTech:
PCIe Gen1/Gen2/Gen3 verification, Ethernet MAC with Wishbone interface, RTL design understanding, ECAM configuration space testing, packet-level transaction validation, coverage-driven verification, scoreboard implementation, testbench modularity improvementProtocols Knowledge:
PCIe (Gen1/2/3), Ethernet (MAC), AXI, Wishbone
DVDV85Bangalore, IndiaSkills:
UVM-based testbench development, constrained-random test generation, functional and code coverage closure, protocol compliance verification, assertion and checker implementation, regression debugging, simulation log and waveform analysis (Verdi), emulation and simulation flow (Zebu, HAPS), register layer integration, verification planning and documentation, collaborative and independent problem-solvingLanguages:
SystemVerilog, VerilogTools:
Synopsys VCS, Mentor Graphics QuestaSim, ModelSim, Verdi, Cadence Xcelium, Synopsys Zebu, Cadence VirtuosoTech:
PCIe Gen1/2/3/4/5 subsystem verification, UCIE VIP development, HDMI/DisplayPort transactor testing, AXI/AMBA protocol compliance, ECAM configuration space testing, scoreboard and assertion implementation, coverage-driven verification, RTL design analysis, testbench modularity improvement, SVA integration, emulation environment setup and test case migrationProtocols Knowledge:
PCIe (Gen1/2/3/4/5), UCIE, HDMI, DisplayPort, AXI, AMBA, Wishbone, Ethernet MAC
DVDV94Bangalore, IndiaSkills:
UVM-based testbench development, constrained-random test generation, functional and code coverage analysis, VIP and IP integration, protocol compliance verification, reference model implementation, scoreboard/checker design, regression testing and debug, documentation of verification plans and results, visual quality and bit-accuracy verification, synthesizability optimization, proactive issue resolutionLanguages:
SystemVerilog, VerilogTools:
QuestaSim, Cadence, Verdi, simulation and debugging tools, coverage analysis toolsTech:
DSC Encoder/Decoder IP verification (VESA), HUB75 Display Driver (FPGA), GNRD Ethernet verification (Intel), avionics verification with DO-254 process (Boeing), VIP & IP conversion to cheetafication (Intel), APB-based design integration, SPI and I2C protocol testing, UVM verbosity migration, entropy coding and compression pipeline verificationProtocols Knowledge:
APB, SPI, I2C, Ethernet, Display Stream Compression (DSC)
DVDV103Bangalore, IndiaSkills:
UVM-based testbench development, constrained-random test generation, functional and code coverage analysis, UART/SPI/I2C protocol verification, AON block and AI microcontroller verification, sensor fusion and wakeup-word signal validation, assertion-based verification, scoreboard/checker design, RTL-level debugging, FSM-based design, regression testing and debug, verification documentation and process improvementLanguages:
SystemVerilog, Verilog, C, Shell ScriptingTools:
QuestaSim, VCS (Synopsys), coverage analysis tools, simulation and debugging toolsTech:
32-bit custom microcontroller verification, AI Neuron and ALU validation, LUT verification, SRAM interface validation, MAC block verification, UART IP core verification, watchdog timer verification, sensor fusion system validation, voice processing with I2S, integration of digital and analog microphones, wakeup-word analysis, standalone IP and SoC level verification environmentsProtocols Knowledge:
UART, SPI, I2C, I2S, AMBA
DVDV112.6Bangalore, IndiaSkills:
UVM-based testbench development, testplan creation, constrained-random test generation, functional coverage development and analysis, SVA-based assertion checks, protocol verification for AXI/APB/UCIe, regression testing using VManager, scoreboard/checker design, RTL-level debugging, lane repair and shift feature verification, reusable UVM component creation (driver, monitor, sequencer), sequence and scenario development, FIFO and SoC-level bus verificationLanguages:
SystemVerilog, Verilog, C, PythonTools:
ModelSim, QuestaSim, Cadence Xcelium, VManager, IMC (Coverage Analysis)Tech:
UCIe protocol-based inter-chiplet communication, AXI and APB protocol SoC-level verification, asynchronous FIFO verification, RISC-V design familiarity, L1/L2 power mode scenarios, lane shifting logic development, clocking and data validity testing, SVA assertion and debug, scoreboard integration, functional simulation, verification closure trackingProtocols Knowledge:
UCIe, AXI, APB, AHB
DVDV122Bangalore, IndiaSkills:
UVM-based testbench development, constrained-random test generation, coverage-driven verification, functional coverage analysis, assertion-based verification using SVA, scoreboard design, RTL-level debugging, regression testing using VManager, IP and sub-block level verification, lane repair feature verification in UCIe, MMPL resolution and PHY retrain scenario validation, FIFO and RAM verificationLanguages:
SystemVerilog, Verilog, C, PythonTools:
Xcelium, Aldec Riviera Pro, VManagerTech:
UCIe protocol-based interconnect verification, asynchronous FIFO verification, AXI protocol verification, dual-port RAM testbench creation, 8086 microprocessor fundamentals, functional simulation and debug, testbench and scenario development, coverage closure analysisProtocols Knowledge:
UCIe, SPI, AMBA APB, AXI
DVDV135.6Bangalore, IndiaSkills:
UVM testbench development, constrained-random verification, functional and code coverage analysis, assertion-based verification (SVA), scoreboard and checker creation, regression testing, debug and root cause analysis, test scenario design, VIP integration, DPI interface development, protocol verification, code review, coverage-driven verification, RTL issue debuggingLanguages:
SystemVerilog, UVM, C/C++, SVA, TCL, PERL (basic knowledge), Linux shell, VimTools:
Cadence Xcelium, Synopsys VCS, Versium Debug, SimVision, Verdi, QuestaSim, vManager, JiraTech:
PCIe Gen 5 PHY verification, UCIe v1.0 & v2.0 protocol verification, AMBA AXI4, I2C, SPI, Q-SPI verification, VIP reuse with DPI interface, SoC subsystem verification, testbench automation, protocol handshaking, data integrity validation, multi-lane PCIe configurations (x1/x4/x8/x16), regression flow integrationProtocols Knowledge:
PCIe Gen 5, UCIe, AMBA AXI4, I2C, SPI, Q-SPI
DVDV143Bangalore, IndiaSkills:
UVM testbench development, constrained-random verification, functional and code coverage analysis, assertion-based verification (SVA), scoreboard and checker creation, regression testing, debug and root cause analysis, test scenario design, VIP integration, DPI interface development, protocol verification, code review, coverage-driven verification, RTL issue debuggingLanguages:
SystemVerilog, UVM, C/C++, SVA, TCL, PERL (basic knowledge), Linux shell, VimTools:
Cadence Xcelium, Synopsys VCS, Versium Debug, SimVision, Verdi, QuestaSim, vManager, Jira, Visual Studio, Programiz C++ Compiler, Xilinx Vivado, EDA-PLAYGROUND, Sentaurus TCADTech:
PCIe Gen 5 PHY verification, UCIe v1.0 & v2.0 protocol verification, AMBA AXI4, I2C, SPI, Q-SPI verification, VIP reuse with DPI interface, SoC subsystem verification, testbench automation, protocol handshaking, data integrity validation, multi-lane PCIe configurations (x1/x4/x8/x16), regression flow integrationProtocols Knowledge:
PCIe Gen 5, UCIe, AMBA AXI4, I2C, SPI, Q-SPI
DVDfteng-202.5+Bangalore, IndiaSkills:
DFT implementation, scan insertion, scan compression, ATPG for stuck-at and at-speed faults, boundary scan, JTAG, DFT architecture planning, design optimization, feasibility and stack analysis, layout review, SI (signal integrity) optimization, BOC packaging, DRAM design expertiseLanguages:
Verilog, SystemVerilog (basic), C/C++, Python (basic), Linux shellTools:
Synopsys Tetramax, Cadence tools (Virtuoso/Layout), HSPICE, Signal Integrity simulators, MS Office (documentation & presentations)Tech:
ATPG pattern generation for stuck-at and transition faults, scan-based DFT methodology, DDR5 DRAM BOC package design, Y53A X8/X16, Y62E X16 development, cross-section and stack-up design, die placement, BGA/PVA netlist routing, collaboration with AI LLM for DFT fault analysisProtocols Knowledge:
JTAG, Boundary Scan (IEEE 1149.x), DDR5
DVDV154.5+IndiaSkills: SoC/IP level verification, UVM-based environment development, functional & code coverage analysis, assertion development, register model (RAL) integration, regression management, verification planning, protocol compliance testing, image/video frame verification, scoreboard development, RTL integration, environment architecture from scratch

Languages: Verilog, SystemVerilog

Tools: Cadence (Xcelium), Siemens Questasim, Modelsim

Tech: UVM methodology, FPGA display verification, ARINC 818 video over fiber, eDP 3D LCD interface, SFAB switch fabric (crossbar & packet buffer), APB, AHB, MIPI CSI-2, pixel/image frame format validation, protocol agents, randomized testing, assertions, SPI, GPIO, DDR, BFM integration

Protocols Knowledge: I2C, APB, AHB, AXI Stream, ARINC 818, eDP, MIPI CSI-2

DVDV161.2+IndiaSkills: SoC/IP level verification, UVM-based environment development, functional & code coverage analysis, assertion development, protocol VIP/UVC creation, testbench architecture from scratch, regression management, verification planning, protocol compliance testing, checker and scoreboard development, RTL integration, constrained random and directed testing, coverage closure, debug using waveform viewers

Languages: Verilog, SystemVerilog

Tools: Siemens Questasim, GVIM

Tech: UVM methodology, testbench creation from scratch, APB3.0/AXI3.0 protocol VIP/UVC development, master-slave VIP integration, dual-port RAM and FIFO verification, functional coverage model implementation, assertions, reference model/checker creation, SystemVerilog constructs, UVM RAL integration, randomized and directed testing, waveform debugging

Protocols Knowledge: APB 3.0, AXI 3.0, I2C, SPI, GPIO, FIFO, Dual Port RAM

DVDV172+IndiaSkills: SoC/IP level verification, UVM-based environment development, functional & code coverage analysis, assertion development, protocol VIP/UVC creation, testbench architecture from scratch, regression management, verification planning, protocol compliance testing, checker and scoreboard development, RTL integration, constrained random and directed testing, coverage closure, debug using waveform viewers.

Languages: Verilog, SystemVerilog.

Tools: Siemens Questasim, GVIM.

Tech: UVM methodology, testbench creation from scratch, APB3.0/AXI3.0 protocol VIP/UVC development, master-slave VIP integration, dual-port RAM and FIFO verification, functional coverage model implementation, assertions, reference model/checker creation, SystemVerilog constructs, UVM RAL integration, randomized and directed testing, waveform debugging.

Protocols Knowledge: APB 3.0, AXI 3.0, I2C, SPI, GPIO, FIFO, Dual Port RAM.

DVDV184IndiaSkills: Functional verification at IP and SoC level, UVM-based environment development, test plan and coverage plan creation, verification plan development, reusable and configurable testbench creation, debugging with VCS and Verdi, constraint random and directed testing, functional coverage modeling, protocol compliance testing, stress tests, error and corner case development, scripting for automation (Python, Shell), mentoring and team collaboration, GLS zero delay and SDF for testbench optimization.

Languages: SystemVerilog, Verilog, C, C++, Python, Shell scripting.

Tools: Synopsys VCS, Verdi, DVE; Mentor QuestaSim; Cadence Xcelium; Version control: SVN, GIT.

Tech: UVM methodology, testbench architecture from scratch, assertion-based checkers, reference model development, protocol VIP integration (MIPI CSI2 Synopsys VIP), system-level scenario creation, DMA configuration, RTL integration, coverage closure, debug with waveform viewers.

Protocols Knowledge: MIPI CSI-2, AMBA AHB/APB, TCP/IP, Ethernet (400 GbE), UDP, CAN, SPI, I2C, UART, DVP.

DVDV194IndiaSkills: SoC and IP level verification, UVM testbench development, functional and code coverage analysis, assertion-based verification (SVA), test plan and verification plan creation, debugging RTL and coverage issues, DFT verification (JTAG, NTL, MBIST, BSCAN), corner case and stress testing, regression management, subsystem and full-chip verification, protocol integration and verification.

Languages: SystemVerilog, Verilog, VHDL, C, C++, Matlab, Python (basic scripting via Linux tools).

Tools: Synopsys VCS, Verdi, SIM Vision, Mentor QuestaSim, V Manager, Perforce, Git.

Tech: UVM methodology, testbench architecture from scratch, SVA assertion development, DFT features verification (JTAG, TAP2AVMM, TAP2APB, TAP2AXI), FIFO UVC development and integration, AXI and Ethernet protocol testbench integration, coverage closure, GLS-based RTL verification, FPGA (Xilinx), ARM processor knowledge.

Protocols Knowledge: JTAG, AXI, APB, Ethernet, FIFO, UDP.

DVDV2020IndiaSkills: IP & SoC verification, UVM testbench development, testplan creation, functional & code coverage closure, assertion development and validation, regression debugging and issue fixing, DFT & protocol verification, scripting for automation and regression, bug tracking (JIRA), verification flow management.

Languages: SystemVerilog, Verilog, C (basic), Python, Perl, Shell scripting.

Tools: Cadence NCSim, Synopsys VCS, Verdi, QuestaSim, Synopsys VIPs (UCIe, DisplayPort, PCIe), Git, Perforce.

Tech: UVM methodology, RAL implementation, regression test suite development, VIP integration, testbench architecture design, protocol verification (SerDes SGMII, DisplayPort 2.1, PCIe PHY, UCIe, AMBA APB/AHB/AXI), SDRAM memory controller verification, assertion-based verification, lock & arbitration testing, sanity checks, error injection, coverage modeling.

Protocols Knowledge: UCIe, PCIe (PHY), SerDes (SGMII), DisplayPort, AMBA (APB, AHB, AXI), I2C, JTAG.

DVDV212.5IndiaSkills: SoC/IP level verification, UVM-based environment development, functional & code coverage analysis, assertion development, protocol VIP/UVC creation, testbench architecture from scratch, regression management, verification planning, protocol compliance testing, checker and scoreboard development, RTL integration, constrained random and directed testing, coverage closure, debug using waveform viewers.

Languages: Verilog, SystemVerilog, Embedded C.

Tools: Siemens QuestaSim, Synopsys VCS, Verdi, DVE, GVIM, KEIL.

Tech: UVM methodology, testbench creation from scratch, APB3.0/AXI3.0/CHI protocol VIP/UVC development, master-slave VIP integration, RISC-V and ARM Cortex-M3 SoC verification, dual-port RAM and FIFO verification, functional coverage model implementation, assertions, reference model/checker creation, SystemVerilog constructs, UVM RAL integration, randomized and directed testing, waveform debugging.

Protocols Knowledge: APB3.0, AXI3.0, CHI, RISC-V, ARMv7-M, DMA, SRAM, AHB-to-APB Bridge, I2C, SPI, GPIO, FIFO, Dual Port RAM.

DVDV222IndiaSkills: SV-UVM test environment development, assertion and coverage-based verification, VIP development from scratch, test plan and test case development, checker and scoreboard creation, functional and code coverage analysis, debugging and problem solving, testbench architecture, protocol compliance verification.

Languages: Verilog, SystemVerilog, C.

Tools: Questasim, Synopsys VCS, Verdi, GVIM, Xilinx ISE.

Tech: UVM methodology, SVUnit testbench, master-slave UVC development, assertion and checker development, functional coverage model implementation, directed and constrained random testing, integration of VIPs, test plan and feature plan creation, regression management, coverage closure using functional and code coverage.

Protocols Knowledge: MIPI M-PHY, AMBA APB, AHB3, AHB5, basics of PCIe.

DVDV234IndiaSkills: IP/VIP/SOC verification, testbench development, assertion and constraint development, RTL functional verification, functional and code coverage analysis, test plan, coverage plan, and checker plan development, testcase writing, protocol specification study, ASIC design flow understanding, design verification techniques.

Languages: Verilog, SystemVerilog, C, Python (basics).

Tools: Vivado, QuestaSim, ModelSim, VCM, GVim, EDA Playground, PyCharm, Synopsys VCS, Verdi, Perforce.

Tech: UVM methodology, testbench architecture from scratch, VIP/UVC development for PCIe Gen3, AXI3, APB protocols, LPDDR5/DDR5 PHY verification, assertion and coverage model implementation, directed and constrained random testing, error injection with callback mechanisms, regression management, functional and code coverage closure.

Protocols Knowledge: PCIe 3.0, DDR5/LPDDR5 PHY, AXI3, APB, UCIe (basic), CHI protocol.

DVDV244IndiaSkills: IP, VIP, SoC verification, testbench development, assertion and constraint creation, RTL functional verification, functional and code coverage analysis, test plan and coverage plan development, checker development, testcase writing, protocol specification analysis, ASIC design flow understanding, debugging and verification techniques, BSDL file generation, regression testing

Languages: SystemVerilog, Verilog, C, Perl (scripting)

Tools: Questa, Verdi, VERDI Debugger, AMD Flow, COMSOL, Tanner EDA, TSpice

Tech: UVM methodology, testbench and test generation, BSCAN/JTAG chain verification, BSDL file creation, multi-mode test execution (I3C, AUX, USB), simulation and debugging, protocol verification for APB, AXI, I2C, JTAG, BSCAN, GIS data verification, regression management

Protocols Knowledge: APB, AXI, I2C, JTAG, BSCAN, I3C

DVDV254IndiaSkills: IP/SOC verification, testbench development, test plan and testcase writing, functional coverage and assertion development, driver, monitor and scoreboard implementation, regression suite creation and maintenance, digital design understanding.

Languages: SystemVerilog, Verilog, C++

Tools: Synopsys VCS, QuestaSim, Verdi, GIT

Tech: UVM methodology, VIP architecture development for APB, AXI, SPI protocols, UVMF testbench generation, error injection scenarios, scoreboarding, constrained random testing, functional coverage closure, regression management.

Protocols Knowledge: APB, AXI, SPI

DVDV264IndiaSkills: Design verification, test plan creation, testcase writing, functional coverage closure, waveform analysis, RTL debugging, regression testing, firmware and RTL simulation integration, protocol verification, debug support.

Languages: SystemVerilog, Verilog, C (basics), Perl (basics)

Tools: Aldec Riviera-PRO, ModelSim, QuestaSim, Verdi, Keil MDK

Tech: UVM methodology, C-based firmware test development, testbench architecture, regression management, scoreboard-based verification, constrained random verification (CRV), coverage-driven verification (CDV), assertion-based verification (ABV).

Protocols Knowledge: AMBA AXI4, APB, Wi-Fi 6 (MAC/PHY-level)

DVDV272.10+IndiaSkills: Functional & IP-level verification, subsystem verification, UVM-based environment development, reusable testbench creation, assertion-based verification (SVA), register-level and protocol-level test development, verification planning & coverage closure, Python-based automation, regression setup & debugging, waveform analysis, bug triaging, log classification & report automation, documentation (test plan, coverage reports), cross-functional collaboration, version control, team coordination.

Languages: SystemVerilog, Verilog, Python, C/C++, English

Tools: VCS, QuestaSim, Verdi, Gvim, Cadence vManager, Git, Perforce, DOORS, ClearQuest, ClearCase, Excel (for automated reports), Linux, Windows

Tech: Flash Subsystem (SSC 300), QSPI Controller, Secure Boot Subsystem, PPMU (Power Policy Management Unit), APB & AXI interface-based IPs, RAL generation, system-level verification automation, planning wizard integration, UVM RAL-based testing, functional & code coverage closure, SVA assertions, regression trend monitoring.

Protocols Knowledge: APB, AXI, QSPI, USB2.0

DVDV2821+IndiaSkills: Functional Verification (IP, Subsystem, SoC), Testbench Architecture (UVM, OVM, VMM, VERA), Verification Planning, Coverage Closure (Functional & Code), Assertion Development, Register Modeling (RAL), Reference Models, Protocol Verification, Debug, Automation (SV, C, Python), Regression Setup, Formal Reviews, Team Leadership & Project Delivery Management.

Languages: SystemVerilog, Verilog, C, Python, Assembly (RISC-V ISA)

Tools: Cadence VIPs, VCS, Questa, Verdi, JIRA, Cadence vManager, E-Manger, GIT, ClearCase, DOORS, UVM RAL, Simulation & Coverage Tools

Tech: RISCV-V IP Verification, Instruction Generators (Google/Chip-Alliance), SPIKE Reference Model, SoC/Sub-system Level UVM Environments, AXI/AHB/APB Bus Integration, DDR2/DDR3 Memory Controller, SRIO, TLP/PCIE, UART, I2C, SPI, I3C, Register Automation, Assertion-based Checking, Sensor Fusion Verification (6-axis sensors), FPGA Flow Validation, TDM/De-skew Logic, S4S Synchronization.

Protocols Knowledge: AMBA – AXI, AHB, APB; PCIe (TLP); DDR2/3; SRIO; I2C, SPI, I3C

DVDV291IndiaSkills: Design Verification (SystemVerilog, UVM), Regression Debugging, Verification Framework Development, Interrupt Testing, Simulation Tools (VCS, QuestaSim, Xcelium, Simvision), Protocol Verification (APB, AHB, AXI, I2C, SPI), UVM RAL, RTL Synthesis, Python, C++

Languages: SystemVerilog, Verilog, Python, C++

Tools: QuestaSim, Synopsys VCS, Xcelium, Simvision, UVM RAL, Xilinx Vivado, Git

Tech: Battery Management Microcontroller (BM MCU) Verification, Peripheral Interrupt Handling, Software Interrupt Testing, Simulation Debug, FPGA Implementation, AMBA Bus Verification, Verification Automation

Protocols Knowledge: APB, AHB, AXI, I2C, SPI

DVDV306+yIndiaSkills: ASIC/SoC Verification, Testbench & Environment Development, UVM (1.1d), SystemVerilog, C/C++, Regression Debug, Functional Coverage, Assertion-Based Verification, Feature Extraction, Test Plan Development, Verification IP Development, Emulation (Palladium Z1), Checker Design, Directed/Random Testing

Languages: SystemVerilog, Verilog, C, C++, Shell, Perl

Tools: VCS, QuestaSim, Verdi, SimVision, Palladium Z1, Git, SVN, Perforce

Tech: NVMe, UFS, SoC/Subsystem Verification, Ethernet MAC/PCS (10Gbps), CAM, APB Bridge, Memory Connectivity Testing, Fault Isolation Reporting, VIP Development (I2C, SPI, APB), Power Estimation, FPGA/Emulation Flow

Protocols Knowledge: Ethernet (10Gbps), AMBA (AXI, AHB, APB), I2C, SPI, CAM

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Staffing Solutions – India

ExperienceSkillsExpertiseProtocols
15SV/UVM, C, GLSIP/SoC/Sub-system Level/GLSModem, GPU, ONFI, ARM Cortex
7.9SV/UVM, CIP/SoC/Sub-system Level/ GLSPCIe, DDR
6.9SV/UVM, C, GLSIP/SoC/Sub-system Level/ Power-awarePCIe
5SV/UVM, CIP VerificationPCIe
5SV/UVM, CIP VerificationCXL
3SV/UVM, CIP VerificationPCIe, UCIe
25SV/UVM, C, FPGAIP/SoC/Sub-system Level5G
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