Security Verification
As systems grow more complex and interconnected, security has become a critical verification challenge rather than an afterthought. Verifying security requirements alongside functional correctness is now essential for building robust, trustworthy designs. Security Verification Zurich is a leading DV Club event focused on modern hardware and SoC security challenges.
Topics include security verification challenges in IPs, complex SoCs and system-scale designs, the impact of threat modelling on verification strategies, and lessons learned from real-world projects.
The discussion will emphasise what works in practice, sharing experiences, techniques, and insights from researchers, engineers and verification professionals dealing with security-critical designs today.
Agenda (GMT)
| Time | Session Description | Presentations | Videos |
|---|---|---|---|
| 12:00 | Arrival, registration, networking, light refreshments | ||
| 13:00 | Speaker 1 – TBA | ||
| 13:30 | Speaker 2 – TBA | ||
| 14:00 | Speaker 3 – TBA | ||
| 14:30 | Speaker 4 – TBA | ||
| 15:00 | Break with refreshments / networking | ||
| 15:30 | Speaker 5 – TBA | ||
| 16:00 | Speaker 6 – TBA | ||
| 16:30 | Speaker 7 – TBA | ||
| 17:00 | Refreshments / networking |
