RISC-V Verification

RISC-V is rapidly transforming the semiconductor landscape with its open and extensible instruction set architecture. As adoption accelerates across industries, the need for robust and scalable verification methodologies has never been more critical.

Join us at DV Club Cambridge as we dive into the latest innovations and challenges in RISC-V verification. This event will bring together leading experts to share real-world insights, best practices, and advanced techniques for verifying RISC-V cores and complex systems. Whether you’re building commercial RISC-V products or exploring open-source initiatives, this is a must-attend for anyone passionate about quality and reliability in hardware design.

Event at a Glance:

  • Fri 5 Jun 2026
  • 12:00 PM – 6:00 PM CEST
  • University of Cambridge 15 J.J. Thomson Avenue, Cambridge, CB3 0FD

Agenda (CEST)

TimeDetails
12:00Arrival, registration, networking, light refreshments
13:00Speaker 1 – TBA
13:30Speaker 2 – TBA
14:00Speaker 3 – TBA
14:30Speaker 4 – TBA
15:00Break with refreshments/networking
15:30Speaker 5 – TBA
16:00Speaker 6 – TBA
16:30Speaker 7 – TBA
17:00Refreshments/networking