Driving flexibility in AI and HPC system design

The Open Compute Project (OCP) announcement introduces the Universal Die-to-Die (D2D) Transaction & Link-Layer specification, now extended to support UCIe. It addresses a persistent challenge in AI/HPC infrastructure: building economically viable, reconfigurable clusters without costly redesigns.

By decoupling upper-level transaction services from the physical layer (PHY), architects can choose the PHY that best meets latency, throughput or cost targets while keeping the software stack and integration flows stable.

What is the Universal D2D Transaction & Link-Layer?

The Universal D2D specification defines a common framework that abstracts and connects multiple chiplet interfaces (including BoW and UCIe) at the packet and link level.

  •       Profiles and Protocol Variants: Map native IP protocols (e.g., AMBA) into transport packets, preserving semantics and interoperability.
  •       Low-latency, low-overhead packetisation: Minimises integration cost and helps deliver near-monolithic performance without heavy bridges or protocol conversions.
  •       Extensibility: The community can add new profiles for compute, memory, and I/O chiplet classes as use cases grow.

Enabling silicon diversity without disruption

Historically, changing a PHY layer forced wide-ranging redesigns. The Universal D2D approach breaks that dependency, making it possible to:

  •       Mix and match chiplets from different vendors in the same design.
  •       Optimise PHY selection for specific workloads without rewriting higher layers.
  •       Reuse proven IP and software stacks, accelerating time-to-market.

This is especially important in AI/HPC clusters, where workloads range from low-latency inference to high-bandwidth training.

Technical highlights for system architects

  •       Profiles & Variants: Standardised mappings for on-die protocols enable interoperability without additional protocol bridges.
  •       PHY abstraction: Decouples the physical layer from transaction and software layers for maximum flexibility.
  •       Flit-Aware D2D Interface (FDI): Streaming in Raw format over UCIe can bypass adapter-layer CRC/Retry for latency-critical paths.
  •       Scalable and portable: Supporting multiple PHY slices, data rates, and process nodes, future-proofing AI/HPC designs.

Table 1: Universal D2D layered architecture (Overview)

OCE Universal D2D ODSA D2D (BoW) UCIe
System interface Profiles / Variants N/A (PCIe/CXL out-of-scope)
Packetisation layer Transaction Layer; Upper Link Layer Protocol-layer operation formats
Bitstream interface LLP FDI Streaming
Adapter layer Lower Link Layer D2D Adapter Layer
Physical interface BoW Interface RDI
Physical layer Physical Layer Physical Layer

Table 1: Universal D2D Layered Architecture in the specification for visually mapping Profiles, packet layers, and PHY interfaces.

Part of a broader OCP AI/HPC ecosystem

This release aligns with OCP’s Open Systems for AI initiative. At the recent APAC Summit, contributions such as Mt Diablo, Deschutes and Scale-up Ethernet were highlighted to strengthen performance, cooling and scale-out capabilities in large-scale AI deployments. The OCP Chiplet Marketplace (launched October 2024) further supports adoption with a catalogue of chiplets, chiplet-aware EDA tools and integration services.

See the Universal D2D T&LL specification (PDF) and related resources for deeper technical detail.

OCP develops Chiplet test and verification White Papers

The OCP’s System-in-Package (SiP) and Chiplet Testing workstreams address the challenges and limitations of advanced packaging techniques and chipletisation through two separate White Papers. The test White Paper identifies new test methodologies and workflows and explains how to integrate them with industry best practices to ensure seamless testing from an individual chiplet to the integrated system. The scope includes structural, functional, software, and ATE testing and alignment with existing and emerging standards to realise an open chiplet marketplace.

Complementing this, the test White Paper identifies the main verification challenges in systems built from multiple chiplets. It suggests possible solutions to those challenges and proposes a roadmap to make future integration easier and more efficient.

These initiatives underpin the Universal D2D specification with robust testing and verification practices, giving designers confidence in building interoperable, multi-vendor AI/HPC systems.

For project-specific guidance on chiplet testing and verification workflows, contact Mike.Bartley@alpinumconsulting.com.

Key takeaways

  •       Universal D2D + UCIe enables silicon diversity while keeping upper layers stable.
  •       Profiles & Variants preserve protocol semantics and speed interoperability.
  •       FDI Raw streaming over UCIe supports latency-critical AI/HPC paths.
  •       Testing & Verification workstreams operationalise the standard for production use.
  •       OCP’s broader initiatives and the Chiplet Marketplace accelerate multi-vendor ecosystems.

To discuss how Universal D2D + UCIe impacts your roadmap, Alpinum Consulting can help align testing and verification with your cluster goals.

 

Author

  • Mike Bartley

    Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification. Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP. Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions:

    Alpinum AI provides tools and automations using Artificial Intelligence to help companies reduce development costs (by up to 90%!)

    Alpinum Services provides RTL to GDS VLSI services from nearshore and offshore centres in Vietnam, India, Egypt, Eastern Europe, Mexico and Costa Rica.

    Alpinum Consulting also provides strategic board level consultancy services, helping companies to grow.

    Alpinum training department provides self-paced, fully online training in System Verilog, UVM Introduction and Advanced, Formal Verification, DV methodologies for SV, UVM, VHDL and OSVVM and CPU/RISC-V.

    Alpinum Events organises a number of free-to-attend industry events

    You can contact Mike (mike@alpinumconsulting.com or +44 7796 307958) or book a meeting with Mike using Calendly (https://calendly.com/mike-alpinumconsulting).