Welcome to the July 2025 edition of the monthly Alpinum newsletter focused on keeping you up to date with the world of Design Verification and AI as well as the latest news on our events and services.

 

INDUSTRY NEWS: DESIGN VERIFICATION & AI

 

Deloitte – 2025 Global Semiconductor Industry Outlook

Deloitte

Siemens EDA – Breaking the Bottleneck: A Smarter Approach to Semiconductor Verification

Siemens blog

Review of Machine Learning for Micro‑Electronic Design Verification

ArXiv

RISC-V AI Chips Will Be Everywhere

IEEE Spectrum

The Evolution of SoC Design

Electronic Design

Ex-Intel Execs Raise $21.5M for RISC-V Chip Startup

Reuters

Ron Black, CEO of Codasip interview

on RISC‑V CPU design verification challenges and ecosystem growth

RISC-V International

Outlook 2025: The Role of RISC-V in Shaping the Future

EE Times Asia

Do's & Don'ts for Chip Verification Engineers

Expertia

Does the world need another CPU architecture?

Semiconductor Engineering

 

ALPINUM EVENTS

Sponsored by: Axelera AI

Tue 23 Sep 2025 12:00 PM - 5:00 PM | High Tech Campus 1A, 5656 AE

This event will explore the cutting-edge design and verification methodologies—such as emulation—needed to ensure these next-generation AI platforms meet performance and reliability demands.

 

Next Event: DVClub Austin

7 Oct 2025 | Austin TX & Online

Accelerating Shift-Left by Leveraging GenAI and Formal Verification for Coverage Closure

Explore how generative AI and formal verification are transforming coverage closure in ASIC design—driving faster time-to-market through smarter, earlier verification strategies.

Next Event: DVClub Israel

27 Oct 2025 | Tel Aviv & Online

Harnessing the Power of AI for Verification

Sponsored by: Intel

Explore how AI is reshaping semiconductor verification—from enhancing validator efficiency and resource optimisation to challenging assumptions about where AI truly adds value.

 

Past event: DVClub Zurich

Presented: 15 July 2025

RISC-V Verification

Sponsored by: ETH Zurich & ZeroRICS

Exploring cutting-edge techniques and challenges in verifying RISC-V cores and complex systems.

Past event: DVClub World

Presented: 25 June 2025

Verifying Chiplet-based Systems

Author

  • Mike Bartley

    Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification.

    Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients . The company was acquired by Tessolve Semiconductors in 2020 and Mike worked at Tessolve as SVP.

    Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions:

    Alpinum AI provides tools and automations using Artificial Intelligence to help companies reduce development costs (by up to 90%!)

    Alpinum Services provides RTL to GDS VLSI services from nearshore and offshore centres in Vietnam, India, Egypt, Eastern Europe, Mexico and Costa Rica.

    Alpinum Consulting also provides strategic board level consultancy services, helping companies to grow.

    Alpinum training department provides self-paced, fully online training in System Verilog, UVM Introduction and Advanced, Formal Verification, DV methodologies for SV, UVM, VHDL and OSVVM and CPU/RISC-V.

    Alpinum Events organises a number of free-to-attend industry events

    You can contact Mike (mike@alpinumconsulting.com or +44 7796 307958) or book a meeting with Mike using Calendly (https://calendly.com/mike-alpinumconsulting).