Mike Bartley

About Mike Bartley

Mike started in software testing in 1988 after completing a PhD in Math, moving to semiconductor Design Verification (DV) in 1994, verifying designs (on Silicon and FPGA) going into commercial and safety-related sectors such as mobile phones, automotive, comms, cloud/data servers, and Artificial Intelligence. Mike built and managed state-of-the-art DV teams inside several companies, specialising in CPU verification.Mike founded and grew a DV services company to 450+ engineers globally, successfully delivering services and solutions to over 50+ clients.Mike started Alpinum in April 2025 to deliver a range of start-of-the art industry solutions:Alpinum AI provides tools and automations using Artificial Intelligence to help companies reduce development costs (by up to 90%!) Alpinum Services provides RTL to GDS VLSI services from nearshore and offshore centres in Vietnam, India, Egypt, Eastern Europe, Mexico and Costa Rica. Alpinum Consulting also provides strategic board level consultancy services, helping companies to grow. Alpinum training department provides self-paced, fully online training in System Verilog, UVM Introduction and Advanced, Formal Verification, DV methodologies for SV, UVM, VHDL and OSVVM and CPU/RISC-V. Alpinum Events organises a number of free-to-attend industry eventsYou can contact Mike (mike@alpinumconsulting.com or +44 7796 307958) or book a meeting with Mike using Calendly (https://calendly.com/mike-alpinumconsulting).

RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
RISC-V

RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug

By Mike Bartley|7th October 2025|RISC-V|

Introduction As a verification engineer working on RISC-V designs, I’ve [...]

RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
Blogs, RISC-V

RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug

By Mike Bartley|1st October 2025|Blogs, RISC-V|

Introduction As a verification engineer working on RISC-V designs, I’ve [...]

Compliance, Certification and Verification: Compare and Contrast
Compliance, Certification and Verification: Compare and Contrast
Blogs, RISC-V

Compliance, Certification and Verification: Compare and Contrast

By Mike Bartley|19th September 2025|Blogs, RISC-V|

Introduction For semiconductor and embedded software stakeholders, clarity around compliance, [...]

Inside RISC-V Verification – A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ Flow
Inside RISC-V Verification – A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ Flow
Blogs, RISC-V

Inside RISC-V Verification – A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ Flow

By Mike Bartley|15th September 2025|Blogs, RISC-V|

Event Context: Verification Futures 2025 | Location: Reading, UK | [...]

Open Compute Project’s Universal D2D Link Layer with UCIe Enables Silicon Diversity in AI Clusters
Open Compute Project’s Universal D2D Link Layer with UCIe Enables Silicon Diversity in AI Clusters
Blogs, General

Open Compute Project’s Universal D2D Link Layer with UCIe Enables Silicon Diversity in AI Clusters

By Mike Bartley|19th August 2025|Blogs, General|

Driving flexibility in AI and HPC system design The Open [...]

RISC-V: What You Need to Know
RISC-V: What You Need to Know
Blogs, RISC-V

RISC-V: What You Need to Know

By Mike Bartley|4th August 2025|Blogs, RISC-V|

This article introduces RISC-V, covering essential concepts to help [...]

Accelerating Innovation: Insights from the FPGA Prototyping Event at Rolls-Royce
Accelerating Innovation: Insights from the FPGA Prototyping Event at Rolls-Royce
2025 FPGA, Blogs

Accelerating Innovation: Insights from the FPGA Prototyping Event at Rolls-Royce

By Mike Bartley|28th July 2025|2025 FPGA, Blogs|

Introduction On 21st May 2025, the Design and Embedded [...]

How Virtual Testing Is Revolutionising Automotive Engineering
How Virtual Testing Is Revolutionising Automotive Engineering
Automotive, Blogs

How Virtual Testing Is Revolutionising Automotive Engineering

By Mike Bartley|21st July 2025|Automotive, Blogs|

Introduction The automotive industry is increasingly adopting virtual testing [...]

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