Our Executive Team

Mike Bartley
Mike BartleyFounder and CEO

Dr Mike Bartley has over 30 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams inside several companies (including STMicroelectronics, Infineon, Panasonic, and the start-up ClearSpeed) and also advised several companies on organisational verification strategies (ARM, NXP, and multiple start-ups). He has been working on the application of artificial intelligence (AI) since using genetic algorithms in 1998 and now helps companies to adopt best practice AI to improve everyday efficiency and customer experience and engagements.

Mike successfully founded and grew a software test and hardware verification services company to 450+ engineers globally, delivering services and solutions to over 50+ clients in various technologies and industries. The company was acquired by Tessolve Semiconductors, a global company with 3000+ employees supporting clients in VLSI, silicon test and qualification, PCB, and embedded product development in multiple vertical industries.

Mike is currently a Senior VP at Tessolve supporting VLSI globally, focusing on helping companies incorporate the latest verification and AI techniques and strategies into their verification flows and building verification teams to support these companies in implementing them on IP and SoC projects. He is also responsible for the Tessolve Centres of Excellence running all R&D projects with Tessolve, including building a new AI capability across all Tessolve products and services.

Mike has a PhD in Mathematics (Bristol University) and nine MScs in various subjects, including management (MBA), software engineering, computer security robotics and AI, corporate finance, and blockchain and digital currency. He is studying part-time for an MSc in quantum computing at the University of Sussex and the use of technology in healthcare at the University of Glasgow, as well as a Stanford Professional Certificate in Artificial Intelligence.

Finally, Mike is an active angel investor and board/strategic advisor, having obtained a Financial Times Non-Executive Director Diploma. He has invested in 25+ tech start-ups since 2017 and advises many of them on both growth and investment strategy, as well as providing board level strategic advice to other companies. He has also studied with the Barcelona Ventures Silicon Valley Investor training.

Dr Michael George Bartley

  • Currently working to define and execute an organisation-wide strategy for the deployment of Artificial Intelligence
  • 10 years of creating and growing a technology service company to 400 employees in Europe, APAC and USA with over $8M annual turnover and $1M profit. Acquired by Tessolve in 2020.
  • 30+ years of full life-cycle experience in software and hardware development for commercial, real-time, embedded and safety-related products including multicore hardware and software products
  • Responsible for defining and managing software test strategies and software roll-out processes, measurable release criteria and objective signoff of numerous complex software/hardware products
  • Management of large development teams and offshore teams
  • Extensive experience of programming and debugging in a variety of languages (such as assembler, C, C++, Java, SQL, Unix scripting (awk, perl, tcl, etc), VHDL, Verilog, System Verilog, UVM and e)
  • Strong academic qualifications (MSc in SW Engineering; Maths PhD; MBA) and professional certificates (ISEB Practitioner Certificates in SW Test Management and Analysis; Prince2)

  • Developed and delivered multiple SW training courses in “Formal Verification” and “SW engineering”
  • Developed and delivered multiple HW training courses including “Advanced Verification Techniques”, “SV/UVM”, “Feature Extraction” and “Formal Verification” for hardware engineers

Feb 20 –

Senior Vice President,Tessolve

Responsible for European P&L. global VLSI sales support, R&D & AI strategy

May 08 – Feb 20

Founder and CEO, Test and Verification Solutions Limited

Developing UK-based self-funded company delivering services in software testing and hardware verification, acquired by Tessolve

June 06 – May 08

Software Test and Hardware Verification Manager, ClearSpeed Technology Plc

Responsible for the test and verification of all ClearSpeed SW & HW products, and the outsourcing of appropriate efforts to achieve that

  • Introduced SW test process & outsourced many activities leading to measurable quality improvements; reduced time to market; cost savings
  • Managed the version control, build and automated test framework, the defect tracking system, plus the development of internal tools.
  • Defined software release criteria
  • Lead the verification of aspects of existing chip Si verification – chip worked first time. Lead strategy for development of next chip.

02 – 06

Software Test and Hardware Verification Manager, Elixent

(now Panasonic)

Responsible for the test and verification of all Elixent SW & HW products

  • Developed an automated test framework (written using make, Perl and other scripting languages) and tests (written in C, Verilog and VHDL) for testing the software toolchain and hardware IP
  • Developed and implemented tools and strategies for test and verification of all Elixent IP products
  • Developed test and verification deliverables (written in C) to help support customer integration of Elixent products

`99 – 02

Hardware Verification Manager,
Infineon Technologies

Responsible for creating a new HW verification team and processes, and for spreading excellent QA practises across Infineon

  • Recruited, developed and managed team of over 35 engineers verifying all Bristol-based designs and many multi-site designs
  • Implemented verification processes employing state-of-the-art techniques and tools such that the Bristol site became recognised as a centre of excellence for functional verification
  • Wrote verification IP using the e language

`94 – `99

Verification Engineer, STMicroelectronics
  • Verification manager for ST40
  • Automated equivalence checking for multiple projects
  • Verification of a 64-bit CPU including development of a significant test generation tool using C++ and use of formal mathematical methods

`93 – `94

Lecturer, Bath College
  • Lecturer in computing

`90 – `93

Software Engineer, Praxis
  • Testing a distributed, real-time system specified in Z and written in C
  • QA team-leader on a client-server petro-carbon accounts system

`88 – `90

Programmer, IPL
  • C and assembler tester and programmer and formal methods expert.

`90 – `99

Lecturer (part-time), Open Uni
  • Java; SW Testing; SW Engineering; Pascal; Formal Methods


2024 M.Sc. Blockchain and Digital Currency (University of Nicosia) DoB 29/7/62
2022 M.Sc. (with Merit) in Data Science, Technology & Innovation (Uni of Edinburgh) Address 23 Consort House
2022 M.Sc. (with Merit) in International Corporate Finance (Uni of Salford) 26 Queensway,
2021 M.Sc. (with Merit) in Intelligent Systems & Robotics (De Montfort Uni) London W2 3RX
2019 M.Sc. (with Merit) in Information Security (Uni of London) Mobile

+44 7796 307958
2008 ISEB Practitioner Certificates in SW Test Mgt & Analysis

2001 MBA (Open Uni) Chairman of the British Computer,
1999 MBA in Technology Management (Open Uni) Society, Bristol (‘91–‘01, ‘10 – ‘15)
1997 M.Sc. in Software Engineering (Open Uni) DVClub, Europe organiser (2008 – )
1988

Ph.D. (thesis on Category Theory) (Bristol Uni)

 High-Tech Sector Chair, WoE LEP
1986 M.Sc. (with distinction) in Logic (Bristol Uni) Chair of External Advisory Board for
1984 Postgraduate Certificate in Education (Bristol Uni) Computer Science, Uniof Bristol
1983 1st Class Hons. Degree in Mathematics (Bristol Uni)

1980 A-levels: Maths (A); Further Maths (A); Physics (A)

Work Based Agile Development; C; SQL; Report Writing; Technical, Quality and Resource Planning; Presentation Skills; Principles of Management; C++; Java; VHDL; Model Based Test Generation; Verilog; Synthesis; Specman; SystemC, System Verilog; OVM;
Open Uni SW Engineering; Computer HW and Operating Systems; Project Management; Switching for Digital Telecommunications; Object-Oriented Software Technology; The Competent Manager; Technology Management; Knowledge Management; Strategic Management; Financial Management

  • DAC – formal poster and “Resistance is Futile”
  • “Experiences in Automating Requirements Based Testing”, TestingExperience, Dec 2011
  • “Knowing When You’re Done with Your Requirements”, NMI Embedded Automotive Event, Nov 2011
  • “Successful adoption of OVM and what we learned along the way”, with S.Holloway, Mentor Verif Horizons, Oct 2011
  • “Benchmarking Functional Verification”, with Mike Benjamin, Mentor Verif Horizons, Oct 2011
  • “Strategic Outsourcing Of Software Testing”, Testing & Finance 2009, Homburg, Germany, June 2009
  • “How to Build & Maintain a Successful Outsourced, Offshored Testing Partnership”, TestingExperience, March 2009
  • Chair & speaker on“Introduction to Low Power Verification” at NMI Low Power verification Conference, Feb 2009
  • “Improved time to market through automated software testing”, TestingExperience, December 2008
  • “How to achieve win-win relation with outsource partner”, Test 2008, Bangalore, India. October 2008
  • “Achieving Agility in Testing through Outsourcing”, Test 2008, Delhi, India. October 2008
  • “Lies, Damned Lies and Hardware Verification”, SNUG Europe, October 2008
  • “How to Boost your Productivity through Outsourcing”, Software and Systems Quality Conference, London, Sept 2008
  • “Outsourcing workshop”, SIGiST, British Computer Society, March 2008
  • “What SW testers can learn from HW verification engineers”, SIGiST, British Computer Society, March 2008
  • “Learning Not to Fear PCI Express Compliance Using a Predictable, Metrics Based Verification Closure Methodology”, CDNLive!, Munich, April 2008.
  • “A comparison of three verification techniques: directed testing, pseudo-random testing and property checking”, Mike Bartley, Darren Galpin and Tim Blackmore. DAC 2002.
  • “Why is verification so hard to plan?”, Mike Bartley. SNUG 2002, Paris.
  • “The Art of Verification”, Mike Bartley. Synopsys Compiler, Europe, September 2001.
  • “Verifying a complex, configurable peripheral using Specman Elite”, Mike Bartley and François Cerisier. Verisity User Group Conference, Munich, 2001.
  • “Verification – it’s all about confidence”, Mike Bartley. SNUG 2001, Munich.
  • “Verification IP: Travelling the Axes of Reuse”, Mike Bartley, IP 2001
  • “Verification IP: Reuse of verification knowledge and tests”, Mike Bartley and Ian Hill. IP2000, Edinburgh.
  • “Use of Formality” at San Jose SNUG 1999.
  • “Case Study: Using formal verification to design the Chameleon microprocessor”, Thomas Goust, Mike Bartley, Geoff Barrett and Frederic Rocheteau, Avant! Electronics Journal (IC Design Automation), August 1998.
  • “Coverage analysis in microprocessor verification”, Mike Bartley. Open University MSc dissertation.
  • “Microprocessor design verification by two-phase evolution of variable length tests”, Jim Smith, Mike Bartley and Terry Fogarty. IEEE International Conference on Evolutionary Computing, 1997.
  • “Functional verification methodology of Chameleon Processor”, C. Berthet et al., DAC 1996.
  • Chapters on SW testing and maintenance for Open University MSc course on “Software Engineering”
  • VDM entry in “Encyclopaedia of Software Engineering”, Jon Wiley & Sons.

Further details

Technology growth experience

I successfully started a self-funded, UK tech services company Test and Verification Solutions (T&VS) in 2008 and grew it to a global $8M+ revenue, $1M+ profit company that was acquired in 2020. As CEO, I put together a strong senior management team along with external advisors and developed an international strategy that enabled the executive to deliver against well-defined targets across the organisation.

T&VS developed a strong consultancy business (in hardware design verification) with 400+ engineers worldwide. T&VS demonstrated “thought leadership” in our chosen niche and this created a very strong brand that helped to attract large, multi-nationals to engage us on large consultancy opportunities with long, follow-on contacts. This involved a number of strategies, including speaking at conferences as well establishing our own well-attended conferences; generating white papers; strong social media presence; being present and often leading on industry bodies; a strong network of partners and suppliers; staying at the leading edge of developments in industry development. We also tried to develop a similar consultancy business on software testing but we were not as successful and faced multiple challenges. My analysis suggests this was due to not being able to create a strong brand against incumbents in a more mature industry (the hardware verification sector was in a growth phase based on increasing device complexity and continuous innovation).

I faced a number of challenges boot-strapping T&VS from 1 person in the UK to 400+ globally. Firstly, I ensured that we always had strong cash flow able to withstand temporary periods of loss as we entered new territories. I also established a strong operational support early on to give me the time to focus on growth through strong global marketing. When entering major new territories, I ensured a strong local management team with an eye on minimising overheads. I also ensured we had a low-cost exit strategy in case the territory did not prove successful. As we grew, I put in place a share option scheme which helped to ensure the senior management team stayed in place through the journey to acquisition (and beyond).

I am now SVP at Tessolve supporting an aggressive growth plan to enable an IPO. Tessolve helps customers to develop and test silicon chips, and then into embedded products. My main roles involve growing sales and delivery capability in Europe, global technical sales supporting, and developing capability in emerging technologies.

Angel Investment Experience

I have been investing in tech start-ups for more than 3 years. My main criteria for investment selection are: the strength of the management team and their prior experience in start-ups and the target sector; analysing the technology and the potential to disrupt the existing target market; the realistic addressable market; the investment documents; and finally the exit plan. My decision is then based on their presentations, investment documents, my analysis of their technology and the target market and, most importantly, discussions with the founder(s) and any existing investors or advisors.

Having invested I stay in regular contact with the team, giving strategic and technology advice as requested. I find it useful to identify and track key metrics against forecast. This includes basic gross revenue; profit/loss; sales; customer acquisition costs and retention; revenue concentration; operational efficiency. A major metric is runway and plans for raising future finance: purpose; size of investment and where they will take the company; valuation and potential dilution. Finally, it is important to see a clear path to possible exits with their expected timescales.

Board Advisory Experience

I have been advising the founders of a technical training company for the past 2 years on a strategy bringing in a new executive team to grow the company and bring investment whilst the founders divest their interests. We have now established a more formal board structure and I am moving forwards as a board advisor.

In 2019, I was appointed Chair of the External Industrial Advisory Board for the Computer Science Department at the University of Bristol. The key role is to ensure that the Board members can make a positive contribution to the strategy and advise on operational issues. I work closely with the Head of Department to present the key strategic aims to the board, explain the objectives for the board members, and set the agenda for each meeting. A large amount of the work needs to be performed in subcommittees and these are established with clear objectives, membership, chair, timescales and reporting frameworks. The Head of Department is appointed for a limited time and so I help to ensure continuity of the boards work

I have served on a number of public committees to provide independent oversight including Chair of the High-Tech Sector Group accountable to the West of England Local Enterprise Partnership. As a team, we were tasked with reviewing strategies to grow high-tech employment in the region and working with local public bodies to deliver on them. I developed appropriate committee meeting behaviours such as objective analysis, openness, full contributions and non-critical challenge. As a Director of the High-Tech Bristol and Bath CIC, I contributed to the development of strategies that are successfully engaging young people and children with computing. We have pivoted this to a charity DigiLocal where I am trustee, providing independent assurance on the appropriate running of the charity. More recently, I am Chair of the External Advisory Board for the Department of Computer Science at the University of Bristol), reviewing and providing advice on a range of subjects including student welfare, academic quality and expansion.