• Standard data types and literals
• Procedures statements and procedural blocks
• Operators
• User-defined data types and structures
• Interfaces
• Hierarchy and connectivity
• Tasks and functions (main differences and main use cases)
• Static arrays
• The main Verilog/SV “gotchas” that can cause bugs
• Overview of the main SV features introduced to support verification
• Clocking blocks
• Random stimulus
• Basic Classes
• Polymorphism and virtualisation
• Class-based random stimulus
• How to use interfaces to improve verification productivity
• Covergroup Coverage
• Queues and Dynamic and Associative Arrays
• Assertion-Based Verification
• SystemVerilog Assertions (SVA)
• Direct Programming Interface (DPI)
• How to improve debug productivity
• How to maximise re-use
• Improving productivity through the use of AI

Commercial simulators supported

• Aldec Riviera-PRO™
• Cadence Incisive®
• Siemens EDA Questa®
• Synopsys VCS®