Verification of high-speed interfaces, including PCIe, MIPI, Bluetooth, ZigBee, UCIe, HBM and TSV
Many of the markets that current chips are destined for are markets that have huge demands for data, such as cloud, AI and automotive.
The data may need to be shared with other chips/chiplets using UCIe, with memories via HBM or TSV for 3D designs, or through communication channels which may be wired such as PCIe or wireless such as wifi, ZigBee and Bluetooth. Photonics and quantum will further complicate the needs further.
These speed requirements complicate interface design and verification. This DVClub will explore the latter.
Agenda (EEST)
| Time | Session Description | Presentations | Videos |
|---|---|---|---|
| 12.00 | Arrival, registration, networking, light refreshments | ||
| 13.00 | Speaker 1 – TBA | ||
| 13:30 | Speaker 2 – TBA | ||
| 14:00 | Speaker 3 – TBA | ||
| 14:30 | Speaker 4 – TBA | ||
| 15:00 | Break with refreshments/networking | ||
| 15:30 | Speaker 5 – TBA | ||
| 16:00 | Speaker 5 – TBA | ||
| 16:30 | Speaker 7 – TBA | ||
| 17:00 | Refreshments & Pizza/networking |
