• Introduction to the UVM library, methodology and Universal Verification Components (UVCs)
• UVM component classes
• Packaging and directory structures
• Overview of the structure of a UVM test bench
• Top level test bench and connecting to a DUT
• Sequence items
  • Data types, constraints
  • Data operations (copy, clone, print, etc.)
• Sequences and sequencers
• The basics of virtual sequencers
• Test and testbench classes
  • Testbench layer
  • Test and test selection
• Reports
• Overview of the simulator and UVM phases
• Creating a simple UVM environment
• Basics of configuration
  • Configuration database (uvm_config_db)
  • Configuration objects
  • How configuration works
• Introduction to the factory
  • Type overrides
• UVM macros (such as uvm_do)
• Introduction to the objection mechanism
• Interfaces
  • Adding tasks, etc
• Introduction to UVCs
• Building a simple scoreboard
• Connecting components with tlm analysis interfaces
• Adding flexibility via the command line using parameters etc
• Register models
• Basic UVM debugging features.

Commercial simulators supported

• Aldec Riviera-PRO™
• Cadence Incisive®
• Siemens EDA Questa®
• Synopsys VCS®