Staffing Solutions – India
| Domain | Code | Years | Country | Main skills |
| DV | DV1 | 5+ | India | Skills: RTL Design, SV-UVM testbench, System Verilog assertions Languages: Verilog, System Verilog, C, Assembly Scripting: Python Protocols: PCIe Gen 4, AMBA (APB, AHB), DDR Tools: Xcelium, VCS, DVE, Verdi, Questa, Xilinx-ISE Key Strengths: Integration, verification plan, functional coverage |
| DV | DV2 | 5+ | India |
“Skills: FPGA/ASIC design and verification, digital signal processing, secure communication systems, RF system integration, timing analysis, lab debugging, test planning, power/performance optimization, system-level integration Languages: Verilog, VHDL, C, C++, MATLAB Experience: 5+ years in FPGA design across research, academic, and corporate projects; strong background in SDR and cryptographic hardware; hands-on lab debugging and signal analysis; end-to-end digital design implementation from RTL to synthesis and verification Tools: Vivado, ModelSim, MATLAB/Simulink, Xilinx ISE, PicoZed, SODAQ, AD9361 Tech: SDR, RF systems, NB-IoT, secure baseband communication, ADC/FFT implementation, FPGA bring-up and testing, embedded signal processing Methodologies: Structured test planning, FPGA prototyping, HDL driver customization, simulation and lab-based validation, performance tuning for power-sensitive applications” |
| Dft | Dfteng-1 | 13+ | India | Skills: Fault modeling, Fault simulation, Fault collapsing, Scan chain insertion Languages: Verilog, System Verilog, C, C++, Python, TCL Experience: Scan insertion, BIST/MBIST insertion, Test coverage improvement Tools: Xcelium, Synopsys VCS, DVE, Verdi, Questa Methodologies: UVM, OVM Protocols: PCIe Gen4, AMBA, DDR |
| Dft | Dfteng-2 | 5.5+ | India | Skills: Integrating DFT solutions, ATE testing, Scan design Experience: Expertise in BSCAN, scan insertion, optimizing silicon yield Tools: Tessent, Synopsys tools Key Achievements: Successful execution on Intel products |
| Dft | Dfteng-3 | 5 | India | Experience: in multiple technology nodes with automotive and AI applications Skills: DFT tools and flow, scan insertion, BIST, MBIST, ATPG Key Strengths: Leadership, training juniors, strong fundamentals in DFT and ASIC cycles |
| Dft | Dfteng-4 | 4+ | India | Skills: Scan insertion, IJTAG, MBIST, ATPG, Test coverage analysis Experience: Simulation debug, working with major EDA tools (Synopsys, Cadence, Mentor) |
| Dft | Dfteng-5 | 6 | India | Skills: Modus ATPG, Xcelium simulations, Tessent MBIST validation Tools: Spyglass, Tessent tools Scripting: Bash, TCL |
| Dft | Dfteng-6 | 3 | India | Skills: Fault modeling, Scan chain insertion, BIST/MBIST analysis Tools: Tessent FastScan, TestKompress, BoundaryScan Experience: Test coverage improvement, Fault simulation, DRC analysis |
| Dft | Dfteng-7 | 8+ | India | Skills: Block-level and full-chip DFT, Synthesis, Low pin scan implementation Experience: Experience in RTL writing and SDC writing |
| Dft | Dfteng-8 | 19+ | India | Skills: End-to-end DFT architecture, Test coverage analysis, Flow development Experience: Team leadership (15-20 members), silicon debug, DoE, RMA closures |
| Dft | Dfteng-9 | 3+ | India | Skills: Fault modeling, Scan chain insertion, BIST/MBIST insertion, ATPG Tools: Tessent FastScan, TestKompress, BoundaryScan Experience: DRC analysis, Test coverage improvement |
| Dft | Dfteng-10 | 11+ | India | Skills: ATPG for SAF, TR mode, Scan insertion, Memory BIST insertion Experience: Functional pattern validation, Simulation debug (Verdi/DVE), IP test vectors Tools: Synopsys/Mentor DFT flow, Formal Property check tools |
| Dft | Dfteng-11 | 4.5+ | India | Skills: DRC analysis, ATPG pattern generation, Scan debugging, Boundary Scan Experience: ROM/Memory validation, Post-silicon debugging |
| Dft | Dfteng-12 | 3 | India | Skills: Fault modeling, Scan chain insertion, BIST/MBIST insertion Tools: Tessent FastScan, TestKompress, BoundaryScan Experience: ATPG pattern generation, Test coverage improvement |
| Dft | Dfteng-13 | 3 | India | Skills: Fault modeling, Scan insertion, BIST/MBIST insertion Tools: Tessent FastScan, TestKompress, BoundaryScan Experience: Fault simulation, Test coverage improvement, RTL/Verilog coding |
| Dft | Dfteng-14 | 4 | India | Skills: IOTEST, UDR instructions, Static/Dynamic fault coverage Experience: Test coverage analysis, IOTEST framework implementation |
| Dft | Dfteng-15 | 8+ | India | Skills: MBIST Insertion, Pattern generation, Test validation Experience: Pre and post-silicon debug, ATPG DRC cleanup Tools: Synopsys, Mentor DFT tools |
| Dft | Dfteng-16 | 10 | India | Skills: Scan Insertion, ATPG, PBIST, Simulations Experience: Using tools like DFTCompiler, DFTMAX, Tetramax, Modus Tools: Xcelium, Verdi, VCS |
| Dft | Dfteng-17 | 12+ | India | Skills: DFT using Synopsys tools, Hardware/Software integration testing Experience: Testing in medical, avionics, automation sectors Tools: NI LabVIEW, Cadence Allegro, Mentor Graphics Protocols: UART, RS-232, RS-485, USB, I2C/SPI |
| Dft | Dfteng-18 | 5+ | India | Skills: DFT Implementation, Scan Insertion, BSCAN Experience: Pre-Si & Post-Si validation, Test Automation Tools: Synopsys Tetramax, TestKompress, VCS Scripting: Python, TCL, Shell |
| Dft | Dfteng-19 | 3+ | India | Skills: Test strategies, fault simulation, test coverage optimization Experience: Contributing to ASIC designs, collaborating with cross-functional teams |
| Dft | InfTeng1 | 4 | India |
Skills: Advanced DFT methodologies (MBIST, LBIST, ATPG, Scan, BSCAN), SoC architecture design, RTL-to-GL synthesis, ATE debug, static timing analysis (STA), logic equivalence checking (LEC), gate-level simulation (GLS), design automation and scripting Languages: Verilog, SystemVerilog, Python, Perl Experience: Design-for-Test implementation and debug across complex SoC designs; synthesis and STA using industry-standard tools; automation and efficiency improvement through scripting; test coverage enhancement for robust silicon validation Tools: Tessent (Siemens), Tetramax (Synopsys), Genus, DesignCompiler, QuestaSim, VCS, PrimeTime, Verdi, Visio, LEC Tech: MBIST, LBIST, ATPG, RTL/GL design and verification, Linux/Unix environments, RTL debug, ATE bring-up Methodologies: Structured DFT planning, Scan Insertion, Clock Domain Crossing, STA/LEC closure, GLS validation |